Introduction to the Atmel AVR Family of Microcontrollers

READING

The AVR Microcontroller and Embedded Systems using Assembly and C
by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi

Sections: 0.3, 0.4, 1.2, 2.1, 2.2, 2.8, 2.9, 3.3

SOURCE MATERIAL

1. Reduced Instruction Set Computer: http://en.wikipedia.org/wiki/Load-store_architecture
2. Atmel AVR: http://en.wikipedia.org/wiki/Atmel_AVR
3. AVR Quick Reference Guide: http://www.atmel.com/dyn/resources/prod_documents/doc4064.pdf
4. ATmega328P Summary (26 pages) http://www.atmel.com/dyn/resources/prod_documents/8161S.pdf
5. Arduino Uno schematic
6. Arduino shield
7. ATmega328P (448 pages) http://www.atmel.com/dyn/resources/prod_documents/doc8161.pdf
8. 8-bit AVR Instruction Set (155 pages) http://www.atmel.com/dyn/resources/prod_documents/doc0856.pdf

WHAT IS A FLIP-FLOP AND A REGISTER

You can think of a D flip-flop as a one-bit memory. As illustrated, the something to remember on the D input of flip-flop is remembered on the positive edge of the clock input.

D Flip-Flop

Truth Table

A register is a collection of flip-flops sharing the same clock input.

4-bit Register

Labs are based on the ATmega32U4 used in the Arduino Leonardo and Nano. The ATmega328P shown here, is used in the Arduino UNO. For instructional purposes, both architectures will be referenced. The ATmega328P is the simpler of the two architectures and the easier to learn.

ATmega328P block diagram adapted from the Atmel datasheet

THE AVR ENGINE

Let’s adopt the analogy used by Charles Babbage when he called his computer an Analytical Engine. For closer look see this article in Wired and ATmega328 Wikipedia page.

Photo of ATmega328P Die

INSTRUCTION SET ARCHITECTURE (ISA)

“The Parts of the Engine”

• The Instruction Set Architecture (ISA) of a microprocessor includes all the registers that are accessible to the programmer. In other words, registers that can be modified by the instruction set of the processor.
• With respect to the AVR CPU illustrated in Figure 5.2, these ISA registers include the 32 x 8-bit general purpose registers, status register (SREG), the stack pointer (SP), and the program counter (PC).

Figure 5.2. AVR Central Processing Unit ISA Registers

AVR CPU CORE ARCHITECTURE

“Features of the Engine” Part I

• Reduced Instruction Set Computer (RISC): The instruction set of the computer and target compiler(s) are developed in concert allowing the optimization of both. In this way, a relatively high performance processor can be realized by “reducing” the amount of work any single instruction needs to do; leading to a simpler hardware design (smaller, faster, and cheaper).
  

  8051 Microcontroller	ATmega328P Microcontroller
  cjne A, 0x99, next	cmp r16, 0x99 brne next

• Mostly 16-bit fixed-length instructions. Instructions have from zero to two operands. Many of today’s RISC microprocessors have up to three operands.
• The Register File of the AVR CPU contains 32 x 8 bit mostly Orthogonal (or identical) General Purpose Registers – instructions can use any register; therefore, simplifying compiler design.
• Load-store memory access. Before you can do anything to data, you must first load it from memory into one of the general-purpose registers. You then use register-register instructions to operate on the data. Finally, you store your answer back into memory.

“Features of the Engine” Part II

• Modified Harvard memory model: A Harvard memory model separates Program and Data memory into separate physical memory systems (Flash and SRAM) that appear in different address spaces. A Modified Harvard memory model has the ability to read/write data items from/to program memory using special instructions. A Princeton memory model computer has only a single address space, shared by both the program and data.
• A Two-stage Instruction Pipeline (fetch and execute) resulting in most instructions being executed in one clock cycle. Consequently, the performance of a 20 MHz processor would approach 20 MIPS (Millions of Instructions Per Second). Compare this with the 8051 Complex Instructions Set Computer (CISC) computer which takes a minimum of 12 clock cycles to execute a single instructions (12 MHz clock = 1 MIPS).
• Simplicity of the computer architecture translates to a faster learning curve and utilization of the machine by the student.

AVR CPU INSTRUCTIONS

“The Language of the Machine”

The Instruction Set of our AVR CPU can be functionally divided (or classified) into five (5) categories.

• Data Transfer instructions are used to Load and Store data to the General Purpose Registers, also known as the Register File.
• • Exceptions are the push and pop instructions which modify the Stack Pointer.
  • By definition these instructions do not modify the status register (SREG).
• Arithmetic and Logic Instructions plus Bit and Bit-Test Instructions use the ALU to operate on the data contained in the general purpose registers .
  • Flags contained in the Status Register (SREG) provide important information concerning the results of these operations.
  • For example, if you are adding two signed numbers together, you will want to know if the answer is correct. The state of the overflow flag (OV) bit within SREG gives you the answer to this question (1 = error, 0 no error).
• As the AVR processor fetches and executes instructions it automatically increments the program counter (PC) so it always points at the next instruction to be executed. Control Transfer Instructions allow you to change the contents of the PC either conditionally or unconditionally.
  • Continuing our example if an error results from adding two signed numbers together we may want to conditionally (OV = 1) branch to an error handling routine.

INSTRUCTION FETCH AND EXECUTE

“The Basic Cycles of the Engine”

Once built, our computer lives to Fetch and Execute instructions, the bread-and-butter of the computer programmer. For this reason, the programmer views the computer as a vehicle for executing a set of instructions. This perspective is codified by the Instruction Set Architecture (ISA) of the computer.

Figure 5.3: The Two Basic States of all Microprocessors

Figure 5.4: AVR CPU Registers and Logic used to Fetch and Execute an Instruction

HARVARD VERSUS PRINCETON MEMORY MODEL INSTRUCTION FETCH CYCLE

The five (5) steps required to fetch an instruction on a CPU incorporating the Princeton memory model is provided here. The key difference between the Princeton and Harvard memory model is the physical seperation of program memory from data memory. For embedded systems the program memory is implemented using FLASH memory. With program memory now isolated from data memory, the instruction fetch cycle is reduced to a single (1) step. What is accomplished in that single step is shown in bold.

1. The CPU presents the value of the program counter (PC) on the address bus and sets the read control line.
2. The Flash program memory looks up the address of the instruction and presents the value on the data bus.
3. The value from the data bus is placed into the instruction register and the CPU clears the read control line. The instruction register now holds the instruction to be executed.
4. The program counter is incremented so it points to the next instruction to be executed.
5. The instruction decoder interprets and implements (executes) the instruction.

Figure 5a: Bus Activity for an Instruction Fetch Cycle for Princeton Memory Models

Figure 5b: Bus Activity for an Instruction Fetch Cycle for Harvard Memory Models

I/O Address Space versus Memory Mapped I/O

• Input and Output ports have traditionally been treated as separate parts of the computer.
• The AVR includes an in instruction to read from an I/O port and an out instruction to write to an I/O port.
• The AVR has 64 I/O registers accessible to these two instructions

Problem: The Atmel ATmega line of Microcontrollers needs more than 64 I/O registers (GPIO, Timers,…)

Solution: Instead of looking at computers having 5 basic elements (Input, Output, ALU, CPU, Memory), you can simplify the design to only three (CPU, ALU, and Memory) now allowing the CPU to access 160 “extended” I/O registers using SRAM instructions like lds (load from SRAM) and sts (store to SRAM).

• This was such a powerful technique that Atmel extended the I/O mapping to include the 32 general purpose registers, the original 64 I/O registers, and the 160 extended I/O registers. The overlaying of the I/O address space with the SRAM address space is shown in the next slide.
• A side benefit of the double mapping is the large number of ways of accessing data within SRAM (addressing modes) versus the limited number of instructions and addressing modes available for accessing the original 64 I/O registers (i.e., in, out).
• It is very important to realize that I/O registers are not contiguous within the address space (I/O or SRAM). The mapping is simply a convenient way of accessing registers physically located in diverse locations within the Silicon chip.

Atmel ATmega328P Memory Model

Figure 6: 8-bit ATmega328P Memory Model
Source: microchip.com

ATMEGA328P I/O MEMORY MAP

Appendix

APPENDIX A PROCESSOR CONTROL AND DATAPATH

Control	Datapath
Component of the processor that commands the datapath, memory, data, I/O devices according to the instructions of the memory	Components of the processor that perform arithmetic operations and holds data

APPENDIX B CALCULATING THE LAST ADDRESS

Given a 16K word (2 bytes / word) memory, what is the last address, in hexadecimal?

• The range of memory addresses, like an unsigned number, is from 0 to 2ⁿ – 1
• We are given the size of our memory in decimal as 16K₁₀. So the first step is to convert this number to a power of 2.
  16K₁₀ = 2⁴ * 2¹⁰ = 2¹⁴, which in binary would be…
• Which then can directly be expressed as a binary number.
  
• So the answer is 0x3FFF
• As a short-cut, if you can convert the memory size to a power of 2, the exponent equals the number of 1 in the answer. By dividing the exponent by 4, you have the number of hex digits which are F (1111₂), with the remainder giving you the most significant hex digit. In our example 4 goes into 14, 3 times with a remainder of 2, where 2 ones (0011₂) equal hexadecimal 3₁₆.

APPENDIX C I/O ADDRESS SPACE VERSUS MEMORY MAPPED I/O

Reading: Your textbook covers memory organization in Section 0.3 “Semiconductor Memory” and I/O Mapping in Section 2.2 “The AVR Data Memory.” The following material covers mapping of the I/O address space in a slightly different way. The material was provided in bullet form earlier in this document.

From Charles Babbage’s Analytical Engine to Dr. Jon Von Neumann’s paper on the EDVAC computer, Input and Output have been treated as separate parts of the computer. Input and Output parts of your PC include the keyboard, mouse, printer, display, etc. To support these “peripheral” devices many microprocessors include a separate I/O address space and instructions for working with the registers contained used to control and access data provided by the peripheral device. For the AVR microcontroller you read an I/O register using an in instruction and write using the out instruction. When Atmel adopted the AVR architecture, they discovered that the 64 I/O registers accessible to these two instructions was insufficient for all the peripheral devices that they were planning on adding to the ATmega line of Microcontrollers. Specifically, they added 160 “extended” I/O registers. However, the AVR microprocessor was only designed for 64 I/O registers. To solve this problem, Atmel turned to an alternative way of working with I/O devices pioneered by Motorola and the 6800 family of processors (among others). Motorola realized that there was no reason to treat input and output devices any different from memory. Now instead of looking at computers having 5 basic elements (Input, Output, ALU, CPU, Memory), you could simplify the design to only three (CPU, ALU, and Memory). Now accessing the 160 “extended” I/O registers was accomplished using SRAM instruction like lds (load from SRAM) and sts (store to SRAM). This was such a powerful technique that Atmel extended the I/O mapping to include the 32 general purpose registers, the original 64 I/O registers, and the 160 extended I/O registers. The overlaying of the I/O address space with the SRAM address space is shown in the next section.

A side benefit of the double mapping is the large number of ways of accessing data within SRAM (addressing modes) versus the limited number of instructions and addressing modes available for accessing the original 64 I/O registers.

It is very important to realize that I/O registers are not contiguous within the address space (I/O or SRAM). The mapping is simply a convenient way of accessing registers physically located in diverse locations within the Silicon chip.

APPENDIX D A BRIEF HISTORY OF THE COMPUTER

4,000 to 3,000 BC Abacus (+, -, *, /)

• The abacus is an instrument used to perform arithmetic calculations. The positions of beads on a set of wires determine the value of the digit. Romans called these beads calculi the plural of calculus, meaning pebble. This Latin root gave rise to the word calculate. In one contest the Abacus easily won over a mechanical calculator. The abacus is still used in China, Japan, and Korea.

1642 Blaise Pascal Mechanical Calculator (+, -)

• Designed at the age of 20. Rotating wheel mechanical calculator with automatic carry between digits on addition and subtraction of decimal digits (like the odometer in a car). In 1671 Baron von Leibnitz created a calculator, which could add, subtract, and multiply.
• A Human Computer with a mechanical calculator can execute 500 operations a day

1833 Charles Babbage and the Analytical Engine

• Conceived by Babbage, the engine established the basic principles upon which modern general-purpose digital computers are constructed. This mechanical machine performed instructions dictated by punched cards, with the variable values being determined by a second set of cards. The punched cards came from Joseph Marie Jacquard’s loom, where they controlled the operation of the weaving machines in 1812.
• Neither the Analytical Engine or Difference Engine (1820), a special purpose computer designed to solve polynomial expressions (ex. N² + N + 41), were ever entirely completed by Babbage known as “the irascible genius.” The difference engine has recently been built as shown here.

1843 Ada Byron and the First Computer Program

• Ada Byron, Lady Lovelace, was one of the most picturesque characters in computer history. Augusta Ada Byron was born December 10, 1815 the daughter of the illustrious poet, Lord Byron. Ada was brought up to be a mathematician and scientist. It was at a dinner party at Mrs. Somerville’s that Ada heard in November 1834, Babbage’s ideas for a new calculating engine, the Analytical Engine. Ada, in 1843, married to the Earl of Lovelace and the mother of three children under the age of eight, wrote an article describing Babbage’s Analytical Engine. Lady Lovelace’s prescient comments included her predictions that such a machine might be used to compose complex music, to produce graphics, and would be used for both practical and scientific use. When inspired Ada could be very focused and a mathematical taskmaster. Ada suggested to Babbage writing a plan for how the engine might calculate Bernoulli numbers. This plan, is now regarded as the first “computer program.” Like her father, she died at 36, Ada anticipated by more than a century most of what we think is brand-new computing.
  Source: http://www.scottlan.edu/lriddle/women/love.htm

1890 Herman Hollerith and the Census Counting Machine

• Hollerith developed punched cards for tabulating equipment used in the 11th census of the United States. Cards contained 288 locations, size of dollar bill in order to save on tooling. Contact brushes completed electrical circuits allowing the system to do: counting, sensing, punching, and sorting. Started Tabulating Machine Company, which turned into the Computer-Tabulating-Recording Company, which turned into the International Business Machine Corporation (IBM) in 1924.

1937 Harvard Mark I

• Howard Hathaway Aiken at Harvard proposed to IBM the Mark I or Automatic Sequence Controlled Calculator — this was to be the first large-scale calculator. Very similar to the Analytical engine, the machine used a combination of electromechanical devices, including many relays. It went to work in 1944 calculating with numbers of 23 digits and computer products of 46-digit accuracy. It received its instructions from perforated tape, from IBM cards, and from the mechanical setting of 1,440 dial switches. Output was either by IBM cards or by typing columns of figures on a roll of paper. The Mark I could perform one division per minute. The machine was in operation for many years, generating many tables of mathematical functions (particularly Bessel functions), and was used for trajectory calculations in World War II.

1943 Electronic Numerical Integrator and Computer (ENIAC)

• Engineers J. Presper Eckert and John W. Mauchly created the ENIAC at the Moore School of Engineering of the University of Pennsylvania between 1943-1946. Built in war time secrecy for the army ordnance department, the ENIAC was designed to do Trajectory calculations. Containing 18,000 vacuum tubes, each accumulator using 100 vacuum tubes arranged as 10 columns of 10 tubes each, the ENIAC could add two 10-digit numbers (the size of ENIAC’s decimal accumulators) in 200 microseconds. Thirty thousand (30,000) times faster than the Mark I. The ENIAC was programmed by patch board and switches. The ENIAC was later moved at a cost of $100,000 to the Ballistic Research Laboratories at the Aberdeen Proving Ground.

1945 Dr. John Von Neumann and the Electronic Discrete Variable Computer (EDVAC)

• EDVAC was the first general-purpose stored program binary electronic (vacuum tube) computer. Completed in 1950 after the EDSAC thus it was not the first operational stored program computer. The technical work done on the EDVAC was by Eckert and Mauchly, Notable the Ultrasonic (or Supersonic) Delay Line, with the logical organization done by Von Neumann, Burke, and Goldstine.
  
• This computer was the blueprint for most modern day computer systems having in it the 5 principle organs that make up almost all modern day computers. Input, Output, Arithmetical, Central Control, Memory (storing both the numerical as well as the instructional information for a given problem), Eckert as well as others left before the EDVAC was ever completed. Architecturally the EDVAC is classified as a general purpose four address computer.

1947 The First Computer Bug

• American engineers have been calling small flaws in machines “bugs” for over a century. Thomas Edison talked about bugs in electrical circuits in the 1870s. When the first computers were built during the early 1940s, people working on them found bugs in both the hardware of the machines and in the programs that ran them.
• In 1947, engineers working on the Mark II computer at Harvard University found a moth stuck in one of the components. They taped the insect in their logbook and labeled it “first actual case of bug being found.” The words “bug” and “debug” soon became a standard part of the language of computer programmers.

1951 John Von Neumann and Princeton’s IAS (Institute for Advance Study) Machine

• Designed to develop a world weather model, the IAS machine incorporated most of the general concepts of parallel binary stored-program computers. That is it used random access memory or parallel memory, CRTs. One address computer.

1951 Eckert and Mauchly and the UNIVAC I

• Soon after the formal dedication of ENIAC computer, J. Presper Eckert and John W. Mauchley’s left the University of Pennsylvania to start their own business. Early orders from U.S. government agencies and other potential customers were not enough to keep the young Eckert-Mauchley Computer Corporation alive, and Remington Rand agreed to purchase the firm in 1950. Work on the UNIVAC I (Universal Automatic Computer) went forward, and the first commercially available electronic (vacuum tube) digital computer was delivered to the Bureau of the Census in early 1951. By 1957, some 46 copies of the machine had been installed at locations ranging from the David Taylor Model Basin of the U.S. Navy Bureau of Ships, to Pacific Mutual Life Insurance Company, to the offices of the Commonwealth of Pennsylvania.
• The UNIVAC, like the ENIAC, had vacuum tube circuit elements. There also were some 18,000 crystal diodes. Central memory was handled in acoustic delay-line tanks, which were used in several early computers. UNIVAC also had an external magnetic tape memory, as well as magnetic tapes used in input and output. Users of UNIVAC played an important role in the development of programming languages. Source: Smithsonian Computer History Collection

1965 Digital Equipment Corporation (DEC) PDP-8

• Designed using Integrated Circuits, DEC sold the first PDP-8 for only $18,000. Later versions of this machine that incorporated improvements in electronics appeared over the next decade. These became steadily smaller and cheaper, triggering a rush of new applications in which the computer was embedded into another system and sold by a third party (called an Original Equipment Manufacturer, or OEM). Some machines were specifically designed for time sharing and for business applications. Ultimately over 50,000 PDP-8’s were sold (excluding those embedded as single chips into other systems) bringing computers into the laboratory and the manufacturing plant’s production line, and thus the minicomputer industry was born. (read “The Sole of a New Machine”).

The x86 isn’t all that complex — it just doesn’t make a lot of sense
Mike Johnson
Leader of the 80×86 Design at AMD
Microprocessor Report (1994)

June 1969 to April 1971 Ted Hoff and Intel 3-chipset 4004

• Intel, a company founded in 1968, is asked by Busicom of Japan to design a custom LSI calculator chip-set. Intel discovers design will take 11 36-40 pin IC packages and proposes a creative alternative. Ted Hoff, at Intel, had been working with the PDP-8 min-computer and proposed to Busicom that a general purpose LSI chip-set be designed that could be programmed to be a calculator or for other applications. We are so used to using computers, that the genus of this step can escape us. The traditional solution was to design what you wanted using logic gates. What Ted Hoff envisioned was a wholly different approach. You design a simple CPU and taught it using software to do what you want. Today these computers are known a microcontrollers and embedded systems. Publicly announced on November 1971.

Nov 1969 to Jan 1972 Vic Poor and the Intel 8008

• Vic Poor of Datapoint Corporation of San Antonio, Texas (manufacturers of “intelligent terminals” and small computer systems) along with Cogar and Viatron engineers design a very elementary computer, and put under contract Intel and Texas Instruments to implement the design on a single logic chip. Intel succeeded, but their product executed instructions approximately ten (10) times as slowly as Datapoint had specified and way behind schedule (work had been stopped by Intel to complete the Busicom chip-set.); so Datapoint declined to buy it, and built their own product using existing logic components. And thus Intel holding a computer-like logic device (whose development had been paid for) marketed the Intel 8008 and the microcomputer industry was born.

1975 John Cocke and the IBM 801

• The first (Reduced Instruction Set Computer) RISC machine was developed as part of the IBM 801 Minicomputer Project. John Cocke contributed many detailed innovations in the 801 processor and associated optimizing compiler, and is considered the “father of RISC architecture.”
• “John’s concept of the RISC resulted from his detailed study of the trade-offs between high performance machine organization and compiler optimization technology. He recognized that an appropriately defined set of machine instructions, program controls, and programs produced by a compiler — carefully designed to exploit the instruction set — could realize a very high performance processor with relatively few circuits. Critical to the success of RISC was the concept of an optimizing compiler able to use the reduced instruction set very efficiently and maximize performance of the machine.”
  Source: http://domino.watson.ibm.com/comm/pr.nsf/pages/news.20020717_cocke.html

1976 Intel i8748

• Prior to 1976 small board computers (SBCs) were designed around microprocessor chips, like the 8080. These SBCs included all the features needed to implement a very simple computer system. These SBCs, of which the D2 by Motorola, KIM-1 by MOS Technology, and SDK-85 by Intel are the most memorable, quickly found their way into design labs at colleges, universities, and electronic companies. By adding peripheral cards these SBCs could read sensors and control actuators. In 1976 Intel put all of the features found on an SBC and parts of the peripheral cards into one chip known as the i8748. With over 17,000 transistors the i8748 was the first device in the MCS-48 family of microcontrollers. This IC, and other MCS-48 devices, quickly became the de facto industrial standard in control-oriented applications. Soon MCS-48 devices were replacing electromechanical components in many modern appliances.

1980 Intel 8051

• With over 60,000 transistors, the power, size, and complexity of microcontrollers moved to the next level with Intel’s introduction of the 8051, the first device in the MCS-51 family of microcontrollers. In a bold move, Intel allowed other manufacturers to make and market code-compatible variants of the 8051. This step led to its general acceptance by the engineering community as the de facto standard in microcontroller architectures.

1996 Atmel AVR

• AVR is a moniker for a family of Atmel 8-bit RISC microcontrollers. The AVR is a Modified Harvard architecture machine with program and data stored in separate physical memory systems that appear in different address spaces. The AVR architecture was conceived by Alf-Egil Bogen and Vegard Wollan at the Norwegian Institute of Technology (NTH). When the technology was sold to Atmel, the internal architecture was further developed by Alf and Vegard at Atmel Norway, a subsidiary of Atmel founded by the two architects. The name AVR sounds cool and does not stand for anything.
  Source: http://en.wikipedia.org/wiki/Atmel_AVR

APPENDIX E CLASSIC COMPUTER ARCHITECTURE

As we discovered in our short history lesson, computers are designed to meet a specific set of requirements. In the early days, these requirements were to meet some military, science, civil, or commercial need. For the military, it was predominately the calculation of ballistic tables; for science to calculate the motion of the planets or the weather. For civil keeping track of people and commercial keeping track of the money. To meet these requirements the computer was conceived and described by its (1) hardware components and (2) the instructions it could execute. The former, for all modern day computers, were codified by Von Neumann in his landmark paper describing the architecture of the EDVAC computer.

Von Neumann’s paper describes a computer architecture having five basic components: Input, Output, Memory, Control, and Arithmetical.

Figure 1-1: A First Draft of a Report on the EDVAC: June 30, 1945

For this class we will Reparation these elements as discussed in the next section and defined in Figure 1-3. An important component of this new viewpoint is the central processing unit (CPU) which will be divided into a Control and a Datapath element as shown in the Figure 1-2. Atmel literature uses the term microcontroller unit (MCU) in place of the more generic central processing unit. In this course the two terms are considered synonymous.

Figure 1-2: High-level View of a CPU

Classic Microcontroller Architecture

The CPU is divided into a Control and a Datapath element as shown in the Figure 1-2. The Control Unit contains combination logic and translates the instructions held in the instruction register (not shown) into the control signals needed to execute the instruction. The data path contains the General Purpose Registers (technically known as the Register File) and the Arithmetic and Logic Unit (ALU). The Datapath includes a few other registers which we will learn about shortly.
The integration of the program and data memory described by Von Neumann is today known as the Princeton memory model. The architecture of our AVR processor separates these two types of memory into Flash Program Memory and Static Random Memory (SRAM). This separation of program and data memory more resembles the Harvard Mark I computer, than the EDVAC computer, and is therefore known as the Harvard memory model.

The input and output functions of Figure 1-1 will be treated together and simply called input/output (I/O). For microcontrollers, the term I/O includes all the Peripherals (Parallel I/O, Counter/Timers, etc.) supported by a particular model of microcontroller, in our case the ATmega328P.

For this class the Von Neumann architecture is thus repartitioned into five basic blocks: Flash Program Memory, SRAM Data Memory, Control Unit, Datapath, and Input-Output.

Figure 1-3: Basic Microcontroller Architectural Elements

APPENDIX F ATMEGA328P ARCHITECTURAL OVERVIEW

Reading: Section 5.1 Overview plus Atmega8 Block Diagram
Clock

• ATmega Family – Up to 20 MHz
• Arduino Duemilanove – 16 MHz (ATmega328P)
• ALU – On-chip 2-cycle Hardware Multiplier

Memory

• ATmega Family – Up to 256 KBytes Flash, 4K Bytes EEPROM and 8K Bytes SRAM.
• ATmega328P – 32 KBytes Flash, 1K Bytes EEPROM, and 2K Bytes SRAM
• Self-Programming Flash memory with boot block (ICSP header)

Peripheral Subsystems

• Two 8-bit (PORTB, PORTD), plus One 7-bit (PORTC) General Digital I/O Ports
• Programmable Serial USART, Master/Slave SPI Serial Interface.
• Byte-oriented 2-wire Serial Interface (TWI) is Philips I2C compliant.
• Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
• One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
• Six PWM Channels
• 8-channel 10-bit A/D converter with up to x200 analog gain stage.
• Programmable Watchdog Timer with Separate On-chip Oscillator
• On-Chip Debug through JTAG or debugWIRE interface.

Other Features

• External and Internal Interrupt Sources with 2 instruction words/vector

Note

• In the following Block Diagram, Power (V_cc), Ground (GND), and the clock input (XTAL) are present but not shown.

APPENDIX G MICROPROCESSOR VERSUS MICROCONTROLLER

APPENDIX H TWO-STAGE INSTRUCTION PIPELINE

Pipelining: A technique that breaks operations, such as instruction processing or bus transactions, into smaller distinct stages or tenures (respectively) so that a subsequent operation can begin before the previous one has completed.

From the Atmel ATmega328P Data Sheet Chapter 6 AVR CPU Core, Section 6.1 Overview and with respect to Figure 6-1 Block Diagram of the AVR Architecture

“In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.”

A pipeline stage begins and ends with a register; controlled by a clock. Between the register(s) is combinational logic. Although counter-intuitive, Flash program memory can be viewed as combinational logic with an address generating a word of data. With respect to our AVR architecture (Figure 6-1) the two registers of interest are the Program Counter (PC) and the Instruction Register (IR). Without pipelining these two registers in the control unit (PC, IR) would require two clock cycles to complete a basic computer operation cycle. Specifically, an instruction is (1) fetched and then (2) executed.

Figure 1-4: Fetch and Execute Cycle of the Atmel ATmega Microcontroller

For most instructions, especially one based on a modified Harvard memory model, program memory is not accessed during the execution cycle. This memory down time could be used to fetch the next instruction to be executed, in parallel with the execution cycle of the current instruction. Here then is an opportunity for pipelining! Figure 10.2 illustrates the idea. The pipeline has two independent stages. The first stage fetches an instruction and places it in the Instruction Register (IR), while the second stage is executing the instruction. This two-stage instruction pipeline is also called instruction prefetch can be found in some of the earliest microprocessors including the Intel 8086

Figure 1-5: Instruction Prefetch of the Intel 8086 Microprocessor

For our RISC architecture most instructions are executed in a single cycle (also known as elemental instructions). In this perfect world where all instructions take one cycle to fetch and one cycle to execute, after an initial delay of one cycle to fill the pipeline, known as latency, each instruction will take only one cycle to complete.

Figure 1-6: Program Execution in an AVR RISC two-Stage Instruction Pipelined Architecture

Forgetting for now the circuit delays attendant with implementing the pipeline (for example the latch), and other complicating issues, our performance would be twice that of a non-pipelined design.

APPENDIX I ATMEGA328P INSTRUCTION SET

The Instruction Set of our AVR processor can be functionally divided (or classified) into the following types:

• Data Transfer Instructions
• Arithmetic and Logic Instructions
• Bit and Bit-Test Instructions
• Branch (Control Transfer) Instructions
• MCU Control Instructions

Addressing Modes: Working with AVR’s Load-Store RISC Architecture

READING
The AVR Microcontroller and Embedded Systems using Assembly and C
by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi

Sections: 2.3, 6.2

LOAD-STORE INSTRUCTIONS AND THE ATMEGA328P MEMORY MODEL

When selecting an addressing mode you should ask yourself where is the operand (data) located within the memory model of the AVR processor and when do I know its address (assembly time or at run time).

Figure 1: 8-bit AVR Instruction Set
Source: atmel.com

LOAD-STORE INSTRUCTIONS AND ADDRESSING MODES

• When loading and storing data we have several ways to “address” the data.
• The AVR microcontroller supports addressing modes for access to the Program memory (Flash) and Data memory (SRAM, Register file, I/O Memory, and Extended I/O Memory).

Figure 2: Load-Store Instructions Table

IMMEDIATE

• Data is encoded with the instruction. Operand is therefore located in Flash Program Memory. This is why technically our memory model is a Modified Harvard.

ldi r16, 0x23 // where ldi = 1110, Rd = 0000₂, and constant K = 00100011₂

• Notice that only four bits (dddd) are set aside for defining destination register Rd. This limits us to 2⁴ = 16 registers. The designers of the AVR processor chose registers 16 to 31 to be these registers (i.e., 16 ≤ Rd ≤ 31).

DIRECT

lds r16, A
sts A, r16

Within the AVR family there are two (2) possible lds/sts instructions. A specific family member will have only one lds/sts combination. The ATmega328P lds/sts instruction is illustrated here with the exception that 5 bits (not 4) encode Rr/Rd. This means all 32 registers are available to the lds/sts instruction.

in r16, PINC
out PORTD, r16

REGISTER-REGISTER INSTRUCTIONS

Data Transfer

• Register-register move byte (mov) or word (movw)

Arithmetic and Logic (ALU)

• Two’s complement negate (neg), Arithmetic add (add, adc, adiw), subtract (sub, subi, sbc, sbci), and multiply (mul, muls, mulsu, fmul, fmuls, fmulsu)
• Logical not (com), and (and, andi, cbr, tst), or (or, ori, sbr), exclusive or (eor)
• Clear (clr), set (ser), increment (inc), decrement (dec)

Bit and Bit-Test

• Register logical shift left (lsl) or right (lsr); arithmetic shift right (asr); and rotate left or right (rol, ror)
• Register swap nibble (swap)
• Register bit load (bld) or store (bst) from/to T flag in the Status Register SREG
• I/O Register Clear (cbi) or set (sbi) a bit
• Clear (clFlag) or set (seFlag) a Flag bit in the Status Register SREG by name (I, T, H, S, V, N, Z, C) or bit (bclr, bset).

REGISTER DIRECT

In the following figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. To generalize, the abstract terms RAMEND and FLASHEND have been used to represent the highest location in data and program space.

com r16

add r16, r17

LOAD-STORE PROGRAM EXAMPLE

Write an Assembly program to add two 8-bit numbers.
C = A + B

lds r16, A ; 1. Load variables
lds r17, B
add r16, r17 ; 2. Do something
sts C, r16 ; 3. Store answer

• Identify the operation, source operand, destination operand in the first Data Transfer instruction.
• Identify the source/destination operand in the Arithmetic and Logic (ALU) instruction.
• What addressing mode is used by the source operand, in the first instruction?
• Show contents of Flash Program Memory (mnemonics)
• Show contents of SRAM Data Memory, assuming variables are stored in sequential memory locations starting at address 0100₁₆.
• Modify the program to leave register r16 unchanged by making a copy (use r15).

SPECIAL TOPIC – HARVARD VERSUS PRINCETON ARCHITECTURE

Princeton or Von Neumann Memory Model
Program and data share the same memory space. Processors used in all personal computers, like the Pentium, implement a von Neumann architecture.
Harvard Memory Model
Program and data memory are separated. The AVR processors among others including the Intel 8051 use this memory model. One advantage of the Harvard architecture for microcontrollers is that program memory can be wider than data memory. This allows the processor to implement more instructions while still working with 8-bit data. For the AVR processor program memory is 16-bits wide while data memory is only 8-bits.

You may have already noticed that when you single step your program in the simulator of AVR Studio it is incremented by 1 each time an instruction is executed. No surprise there right? Wrong. The program memory of the AVR processor can also be accessed at the byte level. In most cases this apparent paradox is transparent to the operation of your program with one important exception. When you want to access data stored in program memory, you will be working with byte addresses not words (16-bits). The assembler is not smart enough to know the difference and so when you ask for an address in program memory it returns its word address. To convert this word address into a byte address you need to multiply it by 2. Problematically we do this by using the shift left syntax of C++ to explicitly tell the assembler to multiply the word address by 2. Remember, when you shift left one place you are effectively multiplying by 2.

With this in mind, we would interpret the following AVR instruction as telling the AVR assembler to convert the word address of label beehives in program memory to a byte address and then to take the low order of the resulting value and put into the source operand of the instruction.

ldi ZL,low(beeHives<<1) // load word address of beeHives look-up

APPENDIX A – ATMEGA328P INSTRUCTION SET

Introduction to AVR Assembly Language Programming II: ALU and SREG

READING
The AVR Microcontroller and Embedded Systems using Assembly and C
by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi

Sections: 2.4, 5.1, 5.2, 6.5

COMPLEMENTARY READING
The following source(s) cover the same material as Chapter 2 of your textbook.
They are provided to you in case you want a different viewpoint.

ATMEL document doc8161 “8-bit AVR Microcontroller with 4/8/16/32K Bytes In-System Programmable Flash” Section 6.3.1: SREG – AVR Status Register

INSTRUCTION SET ARCHITECTURE (REVIEW)

Figure 1: AVR Central Processing Unit ISA Registers

ALU – TWO OPERAND INSTRUCTIONS

• All math (+,-,×,÷) and logic (and, or, xor) instructions work with the Register File (register to register).
• Most math and logic instructions have two operands Rd, Rr with register Rd initially containing one of the values to be operated on and ultimately the result of the operation. The initial contents of Rd are therefore destroyed by this operation.

add Rd, Rr ; Rd = Rd + Rr, You may use any register (R0 – R31).

• Some math and logic operations replace the source register Rr with a constant K. Typically denoted by an “i” postfix.

subi Rd, K ; Rd = Rd – K, You may only registers (R16 – R31).

add, adc, adiw Adds two registers and the contents of the C Flag (adc only) and places the result in the destination register Rd.

sub, sbc, subi, sbci, sbiw Subtracts the source register Rs or constant K from the source/destination register Rr and subtracts with the C Flag (sbc and sbci only) and places the result in the source/destination register Rd. Think of the C Flag as the Borrow bit within this context.

mul, muls, mulsu, fmul, fmuls, fmulsu The multiplicand Rd and the multiplier Rr are two registers containing binary or fractional ( f-prefix) encoded numbers. Both numbers may be unsigned (mul, fmul), or signed (muls, fmuls). Finally, the multiplicand Rd may be signed with the multiplier Rr unsigned (mulsu, fmulsu). The 16-bit unsigned product is placed in R1 (high byte) and R0 (low byte). 

and, andi, or, ori, eor Performs the logical AND, OR, and XOR operations between the contents of register Rd and register Rr or constant K.

ALU – SINGLE OPERAND INSTRUCTIONS

• All single operand math and logic instructions only need a single register and usually the mnemonic alone is enough to tell you what it does.

Mnemonic	Operation	Description
com		One’s complement
neg		Two’s complement
inc		Increment
dec		Decrement
clr		Clear
ser		Set Register, Limited to r16-r31
tst		Test for Zero or Minus

ALU PROGRAM EXAMPLE

Write an Assembly program to implement the polynomial expression
B = A² + A + 41

.INCLUDE
.DSEG
A: .BYTE 1 // 8 bit input
B: .BYTE 2 // 16 bit output

.CSEG

; load

lds r16, A ; r16 with the value of A
clr r17 ; r17 with 0
ldi r18, 41 ; r18 with 41

; do something

mul r16, r16 ; r1:r0 = A^2
add r0, r16
adc r1, r17 ; r1:r0 = A^2 + A
add r0, r18
adc r1, r17 ; r1:r0 = A^2 + A + 41

; store

sts B, r0 ; answer byte ordering
sts B+1, r1 ; is little endian

SREG – AVR STATUS REGISTER

SREG – AVR Status Register

Non ALU

• Bit 7 – I: Global Interrupt Enable
  The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction. The I-bit can also be set and cleared by the application with the sei and cli instructions.
• Bit 6 – T: Bit Copy Storage
  The Bit Copy instructions bld (Bit LoaD) and bst (Bit STore) use the T-bit as source or destination. A bit from a register can be copied into T (R_b -> T) by the bst instruction, and a bit in T can be copied into a bit in a register (T -> R_b) by the bld instruction.

ALU
Signed two’s complement arithmetic

• Bit 4 – S: Sign Bit, S = N ⊕ V
  Bit set if answer is negative with no errors or if both numbers were negative and error occurred, zero otherwise.
• Bit 3 – V: Two’s Complement Overflow Flag
  Bit set if error occurred as the result of an arithmetic operation, zero otherwise.
• Bit 2 – N: Negative Flag
  Bit set if result is negative, zero otherwise.

Unsigned arithmetic

• Bit 5 – H: Half Carry Flag
  Carry from least significant nibble to most significant nibble. Half Carry is useful in BCD arithmetic.
• Bit 0 – C: Carry Flag
  The Carry Flag C indicates a carry in an arithmetic operation. Bit set if error occurred as the result of an unsigned arithmetic operation, zero otherwise.

Arithmetic and Logical

• Bit 1 – Z: Zero Flag
  The Zero Flag Z indicates a zero result in an arithmetic or logic operation.

THE SREG OVERFLOW BIT

• The overflow bit indicates if there was an error caused by the addition or two n-bit 2’s complement numbers, where the n-1 “sign bit” is 1 if the number is negative and 0 if the number is positive. In other words, the sum is outside the range 2n 1 to 2n 1 1.
• Another way to recognize an error in addition is to observe that if you add two numbers of the same sign (positive + positive = negative or negative + negative = positive) then an error has occurred.
• An overflow condition can never result from the addition of two n-bit numbers of opposite sign (positive _ negative or negative + positive).
• Here are examples of all four cases for two 8 bit signed numbers.
  

  Case	A	B	C	D
  	0b6b5b4b3b2b1b0	0b6b5b4b3b2b1b0	1b6b5b4b3b2b1b0	1b6b5b4b3b2b1b0
  	0b6b5b4b3b2b1b0	1b6b5b4b3b2b1b0	0b6b5b4b3b2b1b0	1b6b5b4b3b2b1b0

The variable “b_n” simply indicates some binary value and may be 1 or 0. The index of the carry bit (C_n) is equal to the carry into bit b_n. For example, the carry into b₀ is C₀ and the carry out of an 8-bit register b₇ is C₈.

1. Looking first at Case A, a carry cannot be generated out of the sign bit (C_n+1=0); therefore, if a carry enters the sign bit (C_n=1), the sum will be negative and the answer is wrong.
2. For Case B and Case C no error can occur. Observe that in both case B and C because the numbers are contained in an n-bit (n = 8) register, we know they are in the range -2^n-1 to 2^n-1-1 (-128 to 127 for our two 8-bit numbers). Because one number is positive and the other negative, we further know, the answer must be correct.
3. For Case D, a carry will always be generated out of the sign bit C_n+1=1 (ex. C₈ = 1) with the sign bit itself set to 0; therefore, if a carry does not enter the sign bit C_n=0 (C₇=1) the sum will be positive and the answer will be wrong.

• Here is what we have discovered translated into a truth-table.
  
• Solving for the overflow bit (V) we have,

COMPUTING ALU STATUS REGISTER BITS – ADDITION –

Figure 5: Signed vs Unsigned Addition

COMPUTING ALU STATUS REGISTER BITS – SUBTRACTION –

• For subtract instructions (sub, subi, sbc, sbci, sbiw), including compare instructions (cp, cpc, cpi, cpse), the carry bit is equal to  and
• Assume the subtract instruction sub r16, r17 has just been run by the ATmega328P microcontroller. Complete the table provided. The “difference” column should reflect the contents of register r16 after the subtraction operation (leave the answer in 2’s complement form) and not the actual difference (i.e., if done using your calculator).
  

  			Signed	Unsigned
  r16	r17	difference	relationship	relationship	H	S	V	N	Z	C
  3B	3B	00	+ = +	=	0	0	0	0	1	0
  3B	15	26	+ > +	>	0	0	0	0	0	0
  15	3B
  F9	F6
  F6	F9
  15	F6
  F6	15
  68	A5
  A5	68

• Use AVR Studio simulation software to check your answers.

Introduction to AVR Assembly Language Programming II: Branching

READING
The AVR Microcontroller and Embedded Systems using Assembly and C
by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi

Sections: 3.1

ADDITIONAL READING
Introduction to AVR assembler programming for beginners, controlling sequential execution of the program http://www.avr-asm-tutorial.net/avr_en/beginner/JUMP.html

INSTRUCTION SET ARCHITECTURE (REVIEW)

The Instruction Set Architecture (ISA) of a microprocessor includes all the registers that are accessible to the programmer. In other words, registers that can be modified by the instruction set of the processor. With respect to the AVR CPU illustrated here , these ISA registers include the 32 x 8-bit general purpose resisters, status resister (SREG), the stack pointer (SP), and the program counter (PC).

Data Transfer instructions are used to load and store data to the General Purpose Registers, also known as the Register File. Exceptions are the push and pop instructions which modify the Stack Pointer. By definition these instructions do not modify the status register (SREG).

Arithmetic and Logic Instructions plus Bit and Bit-Test Instructions use the ALU to operate on the data contained in the general purpose registers. Flags contained in the status register (SREG) provide important information concerning the results of these operations. For example, if you are adding two signed numbers together, you will want to know if the answer is correct. The state of the overflow flag (OV) bit within SREG gives you the answer to this question (1 = error, 0 no error).

Control Transfer Instructions allow you to change the contents of the PC either conditionally or unconditionally. Continuing our example if an error results from adding two signed numbers together we may want to conditionally (OV = 1) branch to an error handling routine. As the AVR processor fetches and executes instructions it automatically increments the program counter (PC) so it always points at the next instruction to be executed.

INSTRUCTION SET (REVIEW)

The Instruction Set of our AVR processor can be functionally divided (or classified) into the following parts:

• Data Transfer Instructions
• Arithmetic and Logic Instructions
• Bit and Bit-Test Instructions
• Control Transfer (Branch) Instructions
• MCU Control Instructions

JUMP INSTRUCTIONS

• There are two basic types of control transfer instructions – Unconditional and Conditional.
• From a programmer’s perspective an unconditional or jump instruction, jumps to the label specified. For example, jmp loop will unconditionally jump to the label loop in your program.
• Here are the unconditional control transfer “Jump” instructions of the AVR processor
  

  Direct	jmp, call
  Relative (1)	rjmp, rcall
  Indirect	ijmp, icall
  Subroutine & Interrupt Return	ret, reti

Note:

1. Jump relative to PC + (, where k = 12) PC-2048 to PC+2047, within 16 K word address space of ATmega328P

HOW THE DIRECT UNCONDITIONAL CONTROL TRANSFER INSTRUCTIONS JMP AND CALL WORK

• From a computer engineer’s perspective, a direct jump is accomplished by loading the target address into the program counter (PC). In the example, the target address is equated to label “loop.”
  • To provide a more concrete example, assume the label loop corresponds to address 0x0123 in Flash Program Memory.
  • To execute this instruction, the control logic of central procession unit (CPU) loads the 16-bit Program Counter (PC) register with 0x123.
  • Consequently, on the next fetch cycle it is the instruction at location 0x0123 that is fetched and then executed. Control of the program has been transferred to this address.

Figure 2: JMP & CALL Machine Code Stored in Flash Program Memory

HOW THE RELATIVE UNCONDITIONAL CONTROL TRANSFER INSTRUCTIONS RJMP AND RCALL WORK

• From a computer engineer’s perspective, a relative jump is accomplished by adding a 12-bit signed offset to the program counter (PC) . The result corresponding to the target address. In the example, the target address is equated to label “loop.”
  • To provide a more concrete example, assume the label loop corresponds to address 0x0123 in Flash Program Memory (the target address).
  • An rjmp loop instruction is located at address 0x206. When the rjmp is executed, the PC is currently fetching what it thinks is the next instruction to be executed at address 0x207.
  • To accomplish this jump the relative address (kkkk kkkk kkkk) is equal to 0xF1C (i.e., 0x123 – 0x207).
  • Consequently, on the next fetch cycle it is the instruction at location 0x0123 that is fetched and then executed. Control of the program has been transferred to this address.

Figure 3: RJMP & RCALL Machine Code Stored in Flash Program Memory

BRANCH INSTRUCTIONS

• When a conditional or branch instruction is executed one of two things may happen.

1. If the test condition is true then the branch will be taken (see jump instructions).
2. If the test condition is false then nothing happens (see nop instruction).
   Note: This statement is not entirely accurate. Because the program counter always points to the next instruction to be executed, during the execution state, doing nothing means fetching the next instruction.

• The “test condition” is a function of one SREG flag bit. For example, the branch if equal (breq) or not equal (brne) instructions test the Z flag.

HOW THE RELATIVE CONDITIONAL CONTROL TRANSFER INSTRUCTION BREQ WORKS

• If a relative branch is taken (test condition is true) a 7-bit signed offset is added to the PC. The result corresponding to the target address. In the example, the target address is equated to label “match.”
  • To provide a more concrete example, assume the label nomatch corresponds to address 0x0123 in Flash Program Memory (the target address).
  • A brne nomatch instruction is located at address 0x0112. When the brne instruction is executed, the PC is currently fetching what it thinks is the next instruction to be executed at address 0x0113.
  • To accomplish this jump the relative address (kk kkkk) is equal to 0b01_0000 (i.e., 0x123 – 0x113).
  • Consequently, on the next fetch cycle it is the instruction at location 0x0123 that is fetched and then executed. Control of the program has been transferred to this address.

Figure 4: Branch Changes Position of Pointer Counter

BRANCH INSTRUCTIONS

• All conditional branch instructions may be implemented as brbs s,k or brbc s,k, where s is the bit number of the SREG flag bit. For example brbs 6, bitset would branch to label bitset, if the SREG T bit was set.
• To make your code more readable, the AVR assembler adds the following “alias” instructions.
  • SREG Flag bit is clear (brFlagc) or set (brFlags) by name (I, T, H, S, V, N, Z, C) or bit (brbc, brbs).
  • These SREG flag bits (I, T, H, S, V, N, Z, C) use more descriptive mnemonics.
    • Branch if equal (breq) or not equal (brne) test the Z flag.
    • Unsigned arithmetic branch if plus (brpl) or minus (brmi) test the N flag, while branch if same or higher (brsh) or lower (brlo), test the C flag and are equivalent to brcc and brcs respectively.
    • Signed 2’s complement arithmetic branch if number is less than zero (brlt) or greater than or equal to zero (brge) test the S flag

Skip if …

• Bit (b) in a register is clear (sbrc) or set (sbrs).
• Bit (b) in I/O register is clear (sbic) or set (sbis). Limited to I/O addresses 0-31

Note:

1. All branch instructions are relative to PC + (, where k = 7) + 1  PC-64 to PC+63
2. Skip instructions may take 1, 2, or 3 cycles depending if the skip is not taken, and the number of Flash program memory words in the instruction to be skipped (1 or 2).

CONDITIONAL BRANCH ENCODING

Here is how the brbs, brbc and their alias assembly instructions are encoded.

Figure 6: Branching Machine Code

A CONDITIONAL CONTROL TRANSFER (BRANCH) SEQUENCE

A conditional control transfer (branch) sequence is typically comprised of two (2) instructions.
1. The first instruction performs some arithmetic or logic operation using the ALU of the processor.

• Examples of this first type of instruction includes: cp, cpc, cpi, tst
• These ALU operations result in SREG flag bits 5 to 0 being set or cleared (i.e., H, S, V, N, Z, C).
• To allow for multiple branch conditions to be tested, these instructions typically do not modify any of our 32 general purpose registers.
• The compare instructions cp, cpc, cpi should be used when you want to understand the relationship between two registers. For compare instructions, this is accomplished by performing a subtraction operation  without a destination operand (cp r16,r17 is equivalent to r16 – r17).
• The tst instruction should be used when you want to test if the number in one register is negative or zero. For a test instruction, this is accomplished by performing an and operation with the destination and source registers being the same (tst r16 is equivalent to and r16,r16).

WARNING: The Atmel “Instruction Set Summary” document incorrectly classifies compare instructions (cp, cpc, cpi) as “Branch Instructions.” They should be listed under “Arithmetic and Logical Instructions.” To highlight this inconsistency on Atmel’s part, the tst instruction is correctly listed under “Arithmetic and Logical Instructions.”

2. The second instruction is a conditional branch instruction testing one or more SREG flag bits.

CONDITIONAL BRANCH INSTRUCTION SUMMARY

As mentioned in the previous slide, typically a conditional control transfer instruction follows a compare or test instruction, where some relationship between two registers is being studied. The following table may be used to quickly find the correct conditional branch instructions for these conditions.

A Conditional Control Transfer (Branch) Example

Here is how a high-level language decision diamond would be implemented in assembly.

Figure 7: If Branch Flow Chart

; directions (see note)
.EQU south=0b00 ; most significant 6 bits zero
.EQU east=0b01
.EQU west=0b10
.EQU north=0b11

cpi r16,north ; step 1: Z flag set if r16 = 0b00000011
breq yes ; step 2: branch if Z flag is set

Note: These equates are included in testbench.inc

IMPLEMENTING A HIGH-LEVEL IF STATEMENT

Figure 8: High-level If Branch Flow Chart

• A high-level if statement is typically comprised of…
  • Conditional control transfer sequence (last slide) where the complement (not) of the high-level conditional expression is implemented.
  • High-level procedural block of code is converted to assembly.
• C++ High-level IF Expression
  if (r16 == north) {
  block of code to be executed if answer is yes.
  }
• Assembly Version

cpi r16,north ; Is bear facing north?
brne no ; branch if Z flag is clear (not equal)
block of code to be executed if answer is yes.
no:

IMPLEMENTING A HIGH-LEVEL IF…ELSE STATEMENT

Figure 9: If-else Branch Flow Chart

• A high-level if…else statement is typically comprised of…
  • Conditional control transfer sequence where the complement (not) of the high-level conditional expression is implemented.
  • High-level procedural block of code for yes (true) condition.
  • Unconditional jump over the no (false) block of code.
  • High-level procedural block of code for no (false) condition.
• C++ High-level if…else Expression
  if (r16 == north) {
  block of code to be executed if answer is yes (true).
  }
  else {
  block of code to be executed if answer is no (false).
  }
• Assembly Version

cpi r16,north ; Is bear facing north?
brne else ; branch if Z flag is clear (not equal)
block of code to be executed if answer is yes.
rjmp end_if
else:
block of code to be executed if answer is no.
end_if:

ASSEMBLY OPTIMIZATION OF A HIGH-LEVEL IF…ELSE STATEMENT – ADVANCED TOPIC –

Figure 10: If-else Flow Chart

• If the if-else blocks of code can be done in a single line of assembly then the program flow is modified to guess the most likely outcome of the test.
  • This is possible if the value of a variable (for example the segments of a 7-segment display to be turned on) is the only thing done in each block.
  • This optimized program flow will always execute as fast as the normal if..else program flow (if the guess if wrong) and faster if the guess is correct.
  • This implementation is also more compact and often easier to understand.
• Assembly Version
  
  ; 7-segment display (see note)
  .EQU seg_a=0
  .EQU seg_b=1
  .EQU seg_c=2
  …
  ldi r17,1<
  cpi r16, north ; Is bear facing north?
  breq done
  clear (not equal)
  block of code to be executed if guess was wrong.
  done:

Note: These equates are included in spi_shield.inc

Program Examples: Group A or B – Pseudocode example

• Objective
  Assign the least significant 4 switches on the CSULB shield to group A and the most significant to group B. Based on user input, display A or B based on which group has the higher value. In the event of a tie display E for equal. For this programming problem assume that people choose A 50% of the time, B 40% of the time, and set the switches equal to each other 10% of the time.

• Pseudocode
  
  • Using the ReadSwitches subroutine or reading the I/O ports directly, input group A into register A (.DEF regA = r16) and group B into register B (.DEF regB = r17)
  • Preload the output register (.DEF answer = r18) with the letter A  Guess
  • If (A>B) then go to display answer.
  • Preload the output register with the letter B Guess
  • If (B>A) then go to display answer.
  • Set answer to E and display answer.
• Seven segment display values.
  
• Programming work around by interchanging Rd and Rr.
  

Direction Finder – Two Program Solutions

• Objective

Design a digital circuit with two (2) switches that will turn on one of the rooms 4 LED segments indicating the direction you want your bear to walk

• Direction to Segment Conversion Table
  
• Programmer’s Reference Card
  

Direction Finder – Truth Table Implementation

 lds r16, dir // move direction bits into a working register

 // facing east (segment b)
 bst r16,0   // store direction bit 0 into T
 bld var_B,0 // load r16 bit 0 from T
 bst r16,1   // store direction bit 1 into T
 bld var_A,0 // load r17 bit 0 from T
 com var_A   // B = /A * B
 and var_B, var_A
 bst var_B,0 // store r16 bit 0 into T
 bld spi7SEG, seg_b // load r8 bit 1 from T

Implementation of Boolean expressions for segments a, f, and g (circuit schematic)

Direction Finder – Using Conditional Expressions

lds r16, dir

ldi r17, 1< cpi r16,south ; if bear is facing south then we are done
breq done
ldi r17, 1< cpi r16,west ; if bear is facing west then we are done
breq done
ldi r17, 1< cpi r16,east ; if bear is facing east then we are done
breq done
ldi r17, 1<

done:

mov spi7SEG, r17 ; answer to 7-segment register
call WriteDisplay

Pseudo-Instructions TurnLeft, TurnRight, and TurnAround

Using switches 3 and 2, located on Port C pins 3 and 2 respectively, input an action you want the bear to take. The three possible actions are do nothing, turnLeft, turnRight, and turnAround. Write a subroutine named WhichWay to take the correct action as defined by the following table.

Table 5.2: Truth Table of Turn Indicators

; ————————–
; — Which Way Do I Go? —

call ReadSwitches // input port C pins (0x06) into register r7
bst switch, 3 // store switch bit 3 into T
brts cond_1X // branch if T is set
bst switch, 2 // store switch bit 2 into T
brts cond_01 // branch if T is set

cond_00:

rjmp whichEnd

cond_01:

rcall TurnRight
rjmp whichEnd

cond_1X:

// branch based on the state of switch bit 2
:

cond_10:

:

cond_11:

:

whichEnd:

Warning: The above code is for illustrative purposes only and would typically be found in the main looping section of code not in a subroutine. Do not use this code to implement your lab.

InForest and Implementation of IF…ELSE Expression

• The inForest subroutine tells us if the bear is in the forest (i.e., has found his way out of the maze).
• The rows and columns of the maze are numbered from 0 to 19 (13h) starting in the upper left hand corner.
• When the bear has found his way out of the maze he is in row minus one (-1). The subroutine is to return true (r25:r24 != 0) if the bear is in the forest and false (r25:r24 == 0) otherwise.
• The register pair r25:r24 is where C++ looks for return values for the BYTE data type.

Figure 16: inForest Flow Chart

InForest and Implementation of IF…ELSE Expression – Continued –

; ————————–
; ——- In Forest ——–
; Called from whichWay subroutine
; Input: row Outputs: C++ return register (r24)
; No others registers or flags are modified by this subroutine

inForest:

push reg_F // push any flags or registers modified
in reg_F,SREG
push r16
lds r16,row

test if bear is in the forest

endForest:

clr r25 // zero extend
pop r16 // pop any flags or registers placed on the stack
out SREG,reg_F
pop reg_F
ret

Appendix

APPENDIX A: CONTROL TRANSFER INSTRUCTION ENCODING

Direct

All control transfer addressing modes modify the program counter.

JMP & CALL Machine Code Stored in Flash Program Memory

CONTROL TRANSFER INSTRUCTION ENCODING – Indirect

Indirect Instructions Machine Code

CONTROL TRANSFER INSTRUCTION ENCODING – Relative

Relative Branching Machine Code Stored in Flash Program Memory

APPENDIX B – AVR STATUS REGISTER (SREG)

Status Register

Non ALU

• Bit 7 – I: Global Interrupt Enable
  The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction. The I-bit can also be set and cleared by the application with the sei and cli instructions.
• Bit 6 – T: Bit Copy Storage
  The Bit Copy instructions bld (Bit LoaD) and bst (Bit STore) use the T-bit as source or destination. A bit from a register can be copied into T (R_b  T) by the bst instruction, and a bit in T can be copied into a bit in a register (T  Rb) by the bld instruction.

ALU
Signed two’s complement arithmetic

• Bit 4 – S: Sign Bit, S = N ⊕ V
  Bit set if answer is negative with no errors or if both numbers were negative and error occurred, zero otherwise.
• Bit 3 – V: Two’s Complement Overflow Flag
  Bit set if error occurred as the result of an arithmetic operation, zero otherwise.
• Bit 2 – N: Negative Flag
  Bit set if result is negative, zero otherwise.

Unsigned arithmetic

• Bit 5 – H: Half Carry Flag
  Carry from least significant nibble to most significant nibble. Half Carry is useful in BCD arithmetic.
• Bit 0 – C: Carry Flag
  The Carry Flag C indicates a carry in an arithmetic operation. Bit set if error occurred as the result of an unsigned arithmetic operation, zero otherwise.

Arithmetic and Logical

• Bit 1 – Z: Zero Flag
  The Zero Flag Z indicates a zero result in an arithmetic or logic operation.

APPENDIX C – CONTROL TRANSFER (BRANCH) INSTRUCTIONS

Compare and Test cp, cpc, cpi, tst, bst

Unconditional

• Relative (1) rjmp, rcall
• Direct jmp, call
• Indirect ijmp, icall
• Subr. & Inter. Return ret, reti

Conditional

• Branch if (2) …
  • SREG Flag bit is clear (brFlagc) or set (brFlags) by name (I, T, H, S, V, N, Z, C) or bit (brbc, brbs).
  • These SREG flag bits (I, T, H, S, V, N, Z, C) use more descriptive mnemonics.
    • Branch if equal (breq) or not equal (brne) test the Z flag.
    • Unsigned arithmetic branch if plus (brpl) or minus (brmi) test the N flag, while branch if same or higher (brsh) or lower (brlo), test the C flag and are equivalent to brcc and brcs respectively.
    • Signed 2’s complement arithmetic branch if number is less than zero (brlt) or greater than or equal to zero (brge) test the S flag
• Skip if …
  • Bit (b) in a register is clear (sbrc) or set (sbrs).
  • Bit (b) in I/O register is clear (sbic) or set (sbis). Limited to I/O addresses 0-31

Note:

1. Branch relative to PC + (, where k = 12) + 1 PC-2047 to PC+2048, within 16 K word address space of ATmega328P
2. All branch relative to PC + (, where k = 7) + 1 PC-64 to PC+63, within 16 K word address space of ATmega328P

APPENDIX D – ATMEGA328P INSTRUCTION SET

AVR Control Transfer: Looping

READING
The AVR Microcontroller and Embedded Systems using Assembly and C
by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi

Sections: 3.1, 3.3

ADDITIONAL READING
Introduction to AVR assembler programming for beginners, controlling sequential execution of the program http://www.avr-asm-tutorial.net/avr_en/beginner/JUMP.html
AVR Assembler User Guide

LOOP CONSTRUCTS IN C++ AND ASSEMBLY

Loop Example 1: Loop through a block of code 7 times.

• Typically we increment the counter variable in C++.

for(int i=0; i<7; i++); // This statement loops 7 times {i: 0,1,2,3,4,5,6}

• As shown in the example at the right below, in assembly we decrement the counter variable.
  {i: 7,6,5,4,3,2,1}
  This allows us to immediately test the SREG Z-flag bit without an intermediate compare instruction.

BUTTON DEBOUNCE EXAMPLE

Figure 1: Debounce Timeline Source: http://generichid.sourceforge.net/buttonbounceDSO.png

• In the screen capture (red waveform), a button bounces for about 400us when pressed. Once the transition is detected, we want to design a software loop that will do nothing while the switch input stabilizes.
• Specifically, we want to design a software delay routine that will generate a delay of approx. .

DELAY CALCULATION FOR AVR

We begin by designing a simple loop.

wait:

ldi r16, ____ // Loop Count

delay:

dec r16 // ____ machine cycles
brne delay // ____ machine cycles

To discover the delay generated by our “software” loop we begin by finding the answers to the questions.

• What “Loop Count” L_cnt will generate the maximum delay?
• What is a machine cycle and how many machine cycles are required for each line of code?
• What is the number of machine cycles N_mc in 1 loop?

INSTRUCTION (OR MACHINE) CYCLE TIME FOR THE AVR

• Machine Cycle – The number of clock cycles it takes the CPU to fetch and execute an instruction.
• Because the AVR processors incorporate a 2-stage pipeline, there is a one-to-one relationship between an AVR machine cycle and a clock cycle. In contrast for the non-pipelined 8051 microcontroller one machine cycle = 12 clock cycles.
• Therefore to calculate the time it takes for one machine cycle you only need to take the inverse of the clock frequency.

Example:

• As shown in the “Complete Instruction Set Summary” on page 427 of the AVR Instruction Set Document (Atmel doc0856) most AVR instructions need only one or two clock cycles to fetch and execute an instruction.
  

• Given a clock frequency of 16 MHz and based on the above table a multiple MUL instruction will take

 to execute

• For branch instructions, the answer is not so straight forward.
  

PIPELINING

Before you can fully understand branching and looping you need to understand the concept of pipelining and how it is implemented in our AVR processor.

• Pipelining is a technique that breaks operations, such as instruction processing (fetch and execute) into smaller distinct stages so that a subsequent operation can begin before the previous one has completed.
  
• For most instructions, especially one based on a modified Harvard memory model, program memory is not accessed during the execution cycle. This memory down time could be used to fetch the next instruction to be executed, in parallel with the execution cycle of the current instruction. Here then is an opportunity for pipelining!

AVR INTERSTAGE PIPELINE REGISTERS

• A pipeline stage begins and ends with a register; controlled by a clock. Technically these are known as interstage pipeline registers.
• With respect to our AVR architecture the two registers of interest are the Program Counter (PC) and the Instruction Register (IR).
• Between the register(s) is combinational logic. Although counter-intuitive, Flash Program memory can be viewed as combinational logic with an address generating a word of data.
• Without pipelining these two registers in the control unit (PC, IR) would require two clock cycles to complete a basic computer operation cycle. Specifically, an instruction is (1) fetched and then (2) executed.

AVR TWO-STAGE INSTRUCTION PIPELINE

• The AVR pipeline has two independent stages. The first stage fetches an instruction and places it in the Instruction Register (IR), while the second stage is executing the instruction.

Figure 6: Fetch and Execute Cycle of the Atmel ATmega Microcontroller

• For our RISC architecture most instructions are executed in a single cycle (also known as elemental instructions). In this perfect world where all instructions take one cycle to fetch and one cycle to execute, after an initial delay of one cycle to fill the pipeline, known as latency, each instruction will take only one cycle to complete.

Figure 7: Program Execution in an AVR RISC two-Stage Instruction Pipelined Architecture

BRANCH PENALTY

• Within the context of pipeline architecture, when the execution stage of the pipeline is executing a conditional branch instruction, the execution stage must “predict” the outcome of the instruction in order to fetch what it “guesses” will be the next instruction.
• While on average 80% of the time a branch is taken, the AVR always guesses that the branch will not be taken. This guess is made simply because it is the simplest to implement (the program counter automatically points at the next instruction to be executed).
• When a branch is taken, and the guess is wrong, the processor must build the pipeline from scratch thus accruing a “penalty.” With our simple 2-stage pipeline that penalty is one clock cycle as shown in the AVR Instruction Set Document.
  

BUTTON DEBOUNCE EXAMPLE – CONTINUED

In the screen capture (red waveform), a button bounces for about 400us when pressed. Once the transition is detected, we want to design a software loop that will do nothing while the switch input stabilizes. To remove the noise, we will design a software delay routine that will generate a delay of approx. 500 us.

DELAY CALCULATION FOR AVR

• Returning to our simple software loop

wait:

ldi r16, ____ // Loop Count

delay:

dec r16 // 1 clock cycle
brne delay // + 2 cycles if true, 1 cycle if false

 = Delay generated by the loop
 = period of one machine cycle =  (note: 1 machine cycle = 1 clock cycle) = 1 / 16 MHz = 0.0625 usec
 = number of machine cycles in 1 loop = 3 (for brne N_mc = 2 cycles, we subtract 1 for the one cases where our guess is correct.)
 = number of times loop is run (Loop Count) = ?

CALCULATING MAXIMUM DELAY

• Next we will calculate the maximum delay

 = 0 which results in a count of 256

(approx) Note: the -1 is subtracting the one true result

• Now Let’s increase this delay by adding a nop instruction and then recalculating the maximum delay

 = number of machine cycles in 1 loop = 4

wait:

clr r16 // 0 = maximum delay

delay:

nop // 1
dec r16 // 1 clock cycle
brne delay // + 2 cycles if true, 1 cycle if false

(approx) with r16 = 0 (clr r16)

CALCULATING LOOP COUNT FOR A GIVEN DELAY

• To generate a delay of 500 µs we will initialize r16 for a delay of 50 µs and then write an outside loop that will run the inside loop 10 times for a total delay of approximately 500 µs
• Solving our T_max equation for Loop Count L_cnt

• Set L_cnt for a delay of 50 µsec

wait:

ldi r16, 0xC8 // 200

delay:

nop // 1
dec r16 // 1 clock cycle
brne delay // + 2 cycles if true, 1 cycle if false

LOOP INSIDE A LOOP DELAY

On your own, create an outside loop with a count of 10 to give us a delay of approximately 500 µsec (Hint see Example 3-18 in your textbook)

DESIGN EXAMPLE WITH EE346 SHIELD

When the user presses the button, read first 3 switches (least significant), if the number is less than or equal to 5 then calculate factorial. If greater than 5 turn on decimal point. Display the least significant 4 bits of the answer.

MY DESIGN STEPS

Step 1: Initialized Ports
Step 2: Turned on LED 0 to indicate initialization complete
Step 3: Wrote code to pulse the clock
Step 4: Read in pin waiting for button to be pressed (Loop Example 1)
Step 5: Need to filter out Bounce (Loop Example 2)
Maximum delay that could be generated was only 48 usec
Step 6: Added a NOP instruction, max delay was now 64 usec
Set delay for nice even number of 50 usec
Step 7: Made an outside loop of 10 (Loop Example 3)
Step 8: Converted loop to a subroutine so I could change condition to button release.
Step 9: Check for button pressed and then released
Step 10: Read Switch and check if less than or equal to 6
Step 11: Calculate Factorial (Loop Example 4)
Step 12: Store 4 digit answer to SRAM (SRAM Indirect Addressing Mode)
Step 13: Sequentially, Load each digit and … (SRAM Indirect Addressing Mode)
Step 14: convert to 7-segment display (Flash Program Indirect Addressing Mode)

CSULB PROTO-SHIELD SCHEMATIC

CONFIGURE GPIO PORTS

ATMEGA328P INSTRUCTION SET

Interrupts and 16-bit Timer/Counter 1: ATmega Interrupts

READING

The AVR Microcontroller and Embedded Systems using Assembly and C
by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi

Sections: 10.1, 10.4

Interrupt Basics

Figure 1: Outline of Instructions

• A microcontroller normally executes instructions in an orderly fetch-execute sequence as dictated by a user-written program.
• However, a microcontroller must also be ready to handle unscheduled, events that might occur inside or outside the microcontroller.
• The interrupt system onboard a microcontroller allows it to respond to these internally and externally generated events. By definition we do not know when these events will occur.
• When an interrupt event occurs, the microcontroller will normally complete the instruction it is currently executing and then transition program control to an Interrupt Service Routine (ISR). These ISR, which handles the interrupt.
• Once the ISR is complete, the microcontroller will resume processing where it left off before the interrupt event occurred.

Figure 2: Outline of Instructions with an Interrupt Service Routine

The Main Reasons You Might Use Interrupts

• To detect pin changes (eg. rotary encoders, button presses)
• Watchdog timer (eg. if nothing happens after 8 seconds, interrupt me)
• Timer interrupts – used for comparing/overflowing timers
• SPI data transfers
• I2C data transfers
• USART data transfers
• ADC conversions (analog to digital)
• EEPROM ready for use
• Flash memory ready

ATmega328P Interrupt Vector Table

• The ATmega328P provides support for 25 different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector located at the lowest addresses in the Flash program memory space.
• The complete list of vectors is shown in Table 11-6 “Reset and Interrupt Vectors in ATMega328P. Each Interrupt Vector occupies two instruction words.
• The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0.

ATmega328P Interrupt Vector Table

ATmega328P Interrupt Processing

• (1) When an interrupt occurs, (2) the microcontroller completes the current instruction and (3) stores the address of the next instruction on the stack
• It also turns off the interrupt system to prevent further interrupts while one is in progress. This is done by (4) clearing the SREG Global Interrupt Enable I-bit.
  
  

  Figure 3: Status Register

• The (5) Interrupt flag bit is cleared for Type 1 Interrupts only (see the next page for Type definitions).
• The execution of the ISR is performed by (6) loading the beginning address of the ISR specific for that interrupt into the program counter. The AVR processor starts running the ISR.
• (7) Execution of the ISR continues until the return from interrupt instruction (reti) is encountered. The (8) SREG I-bit is automatically set when the reti instruction is executed (i.e., Interrupts enabled).
• When the AVR exits from an interrupt, it will always (9) return to the interrupted program and (10) execute one more instruction before any pending interrupt is served.
• The Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

push reg_F
in reg_F,SREG
:
out SREG,reg_F
pop reg_F

By The Numbers

Figure 4: Interrupt Process Diagram

Type 1

• The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine.
  • The SREG I-bit is automatically set to logic one when a Return from Interrupt instruction – RETI – is executed.
• There are basically two types of interrupts…
  • The first type (Type 1) is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag.
    • If the same interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software (interrupt cancelled).
    • Interrupt Flag can be cleared by writing a logic one to the flag bit position(s) to be cleared.
  • If one or more interrupt conditions occur while the Global Interrupt Enable (SREG I) bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set on return (reti), and will then be executed by order of priority.

Type 2

• The second type (Type 2) of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

Figure 5: Type 2 Interrupt Process

When Writing an Interrupt Service Routine (ISR)

• As a general rule get in and out of ISRs as quickly as possible. For example do not include timing loops inside of an ISR.
• If you are writing an Arduino program
  • Don’t add delay loops or use function delay()
  • Don’t use function Serial.print(val)
  • Make variables shared with the main code volatile
  • Variables shared with main code may need to be protected by “critical sections” (see below)
  • Toggling interrupts off and on is not recommended. The default in the Arduino is for interrupts to be enabled. Don’t disable them for long periods or things like timers won’t work properly.

Program Initialization and the Interrupt Vector Table (IVT)

• Start by jumping over the Interrupt Vector Table

RST_VECT:

rjmp reset

• Add jumps in the IVT to your ISR routines

.ORG INT0addr // 0x0002 External Interrupt 0

jmp INT0_ISR

.ORG OVF1addr

jmp TOVF1_ISR

• Initialize Variables, Configure I/O Registers, and Set Local Interrupt Flag Bits

reset:

lds r16, EICRA // EICRA Memory Mapped Address 0x69
sbr r16, 0b000000010
cbr r16, 0b000000001
sts EICRA, r16 // ISC0=[10] (falling edge)
sbi EIMSK, INT0 // Enable INT0 interrupts

• Enable interrupts at the end of the initialization section of your code.

sei // Global Interrupt Enable

loop:

The Interrupt Service Routine (ISR)

; — Interrupt Service Routine —
INT0_ISR:

push reg_F
in reg_F,SREG
push r16
; Load
; Do Something
; Store
pop r16
out SREG,reg_F
pop reg_F
reti

; ——————————————————-

Predefined Arduino IDE Interrupts

• When you push the reset button the ATmega328P automatically runs an Arduino Boot program located in a separate Boot Flash section at the top of program memory. If compiled within the Arduino IDE, the Boot program loads your compiled program with these interrupts enabled.

• The millis() and micros() function calls make use of the “timer overflow” feature utilize timer 0. The ISR runs roughly 1000 times a second, and increments an internal counter which effectively becomes the millis() counter (see On your own question).

• The hardware serial library uses interrupts to handle incoming and outgoing serial data. Your program can now be doing other things while data in an SRAM buffer is sent or received. You can check the status of the buffer by calling the Serial.available() function.
• On your own. Given that you are using 8-bit Timer/Counter 0, you have set TCCR0B bits CS02:CS01:CS00 = 0b011 (clk_I/O/64), and the system clock f_clk = 16 MHz, what value would you preload into the Timer/Counter Register TCNT0 to get a interrupt 1000 times a second.

Source: Gammon Software Solutions forum – this blog also covers how to work with all the interrupts in C++ and the Arduino scripting language.

Appendix

The Real World of External Interrupts

Reading

The AVR Microcontroller and Embedded Systems using Assembly and C
by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi

Sections: 10.3, 10.5

External Interrupts

• Review ATmega328P Interrupts Lecture Notes page 4 “Interrupt Basics”
• External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23..0 pins
• 23 Pin Change Interrupts are mapped to the 23 General Purpose I/O Port Pins:

Port B Group		PCINT7 (PB7)  PCINT0 (PB0)
Port C Group	PCINT15 (PC7)	PCINT14 (PC6)  PCINT8 (PC0)
Port D Group		PCINT23 (PD7)  PCINT16 (PD0)

Figure 1: ATmega328P Pinout

ATmega328P Interrupt Vector Table

ATmega328P External Interrupt Sense Control

• The INT0 and INT1 interrupts can be triggered by a low logic level, logic change, and a falling or rising edge.
  
  

  Figure 2: External Interrupt Control Register A

• This is set up as indicated in the specification for the External Interrupt Control Register A – EICRA as defined in Section 12.2.1 EICRA of the Datasheet. The number “n” can be 0 or 1.

ATmega328P External Interrupt Enable

• All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register (SREG) in order to enable the interrupt.
  
  

  Figure 3: Status Register

• The ATmega 328P supports two external interrupts which are individually enabled by setting bits INT1 and INT0 in the External Interrupt Mask Register (Section 12.2.2 EIMSK).
  
  

  Figure 4: External Interrupt Mask Register

• Let’s look at an example. When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
  
  

  Figure 5: External Interrupt Flag Register

• Alternatively, the flag can be cleared by writing a logical one to it. The EIFR register is within the I/O address range (0x00 to 0x1F) of the Set Bit in I/O Register (SBI) Instruction. This flag is always cleared when INT0 is configured as a level interrupt.

When Will External Interrupts be Triggered?

When the INT0 or INT1 interrupts are enabled and are configured as low level triggered (Type 2), the interrupts will trigger as long as…

1. The pin is held low.
2. The low level is held until the completion of the currently executing instruction.
3. The level is held long enough for the MCU to completely wake-up (assuming it was asleep).
   – Low level interrupt on INT0 and INT1 are detected asynchronously (no clock required). The I/O clock is halted in all sleep modes except idle mode. Therefore low level interrupts can be used for waking the part from all sleep modes.
4. Among other applications, low level interrupts may be used to implement a handshake protocol.

When the INT0 or INT1 interrupts are enabled and are configured as edge or logic change (toggle) triggered, (Type 11) the interrupts will trigger as long as…

1. The I/O clock is present.
   – This implies that these interrupts cannot be used for waking up the part from sleep modes other than idle mode.
2. The pulse lasts longer than one I/O clock period. Shorter pulses are not guaranteed to generate an interrupt.

PIN Change Interrupts

• In addition to our two (2) external interrupts, twenty-three (23) pins can be programmed to trigger an interrupt if there pin changes state.
• These 23 pins are in turn divided into three (3) interrupt groups (PCI 2:0) corresponding to the three GPIO Ports B, C, and D
• Each of the groups are assigned to one pin change interrupt flag (PCIF) bit (2:0).
• A pin change interrupt flag will be set, if the interrupt is enabled (see How to Enable a Pin Change Interrupt), and any pin assigned to the group changes state (toggles).

Figure 6: Pin Change Interrupt Register

How a PIN Change Interrupt Works

Here is how it works…

How to Enable a PIN Change Interrupt

In addition to our two (2) external interrupts, twenty-three (23) pins PCINT 23:16, 14:0 can be programmed to trigger an interrupt if there pin changes state. These 23 pins are divided into three (3) interrupt groups (PCI 2:0) of eight (8), seven (7) and (8). Consequently to enable and individual pin change interrupt 3 interrupt mask bits must be set to one (1).

1. The SREG global interrupt enable bit I
2. The pin change interrupt enable bit (PCIE 2:0) group the pin is assigned. Specifically, a pin change interrupt PCI2 will trigger if any enabled PCINT23..16 pin toggles. A pin change interrupt PCI1 will trigger if any enabled PCINT14..8 pin toggles. A pin change interrupt PCI0 will trigger if any enabled PCINT7..0 pin toggles.
   
   

   Pin Change Interrupt Control Register

3. The individual pin change interrupt enable mask bit assigned to the pin (PCINT 23:0) is set. These mask bits are located in the three pin change mask registers assigned to each group.
   
   

   Pin Change Mask Register 2

   
   
   

   Pin Change Mask Register 1

   
   
   

   Pin Change Mask Register 0

ATmega328P Interrupt Processing (REVIEW)

Programming the Arduino to Handle External Interrupts

• Stop compiler optimization of variables within an ISR by adding the volatile qualifier. This keeps the current value in SRAM until needed.

const byte pin = 8; // green LED 0
volatile int state = LOW;

• Add jumps in the IVT to ISR routine, configure External Interrupt Control Register A (EICRA), and enable local and global Interrupt Flag Bits.
  
• Write Interrupt Service Routine (ISR)

void blink()
{

state = !state;

}

To disable interrupts globally (clear the I bit in SREG) call the noInterrupts() function. To once again enable interrupts (set the I bit in SREG) call the interrupts() function.

Programming the Arduino to Handle Interrupts

• In the AVR-GCC environment upon which the Arduino language is built, the interrupt vector table (IVT) is predefined to point to interrupt routines with predetermined names (see “ATmega328P Interrupt Vector Table” on page 6).
• You create an ISR by using the Macro ISR() and these names.

#include <avr/interrupt.h>

ISR(ADC_vect)
{
// user code here
}

• Now that you have defined the ISR you need to locally and globally enable it. Here are the relevant links for learning how to complete your ISR definition.
  • Global manipulation of the interrupt flag
  • Gammon Software Solutions forum – Interrupts
  • ISR() macro

Practice Problems

Design Example – Switch Debounce

• When you press a button, its contacts will open and close many times before they finally stay in position. This is known as contact bounce.
• Depending on the switch construction, this mechanical contact bounce can last up to 10 or 20 milliseconds. This isn’t a problem for lamps, doorbells and audio circuits, but it will play havoc to with our edge-triggered interrupt circuitry.
  
  

  Switch Bounce

• With respect to the waveform above, a switch debounce solution must be designed to filter out these transitions.

Switch Debounce Solutions

So how can we design a “Debounce Circuit” to filter out these transitions.

1. The lowest-cost solution requires no hardware. Specifically, we disable the external interrupt during the switch bounce time. This solution has been implemented for the Arduino by Nick Gammon with Arduino code provided here in the “Example code of a pump timer” section.
2. For some simple electrical solutions visit http://www.patchn.com/Debounce.htm.
3. For our solution, I added a D flip-flop which is clocked at a frequency less than 50 Hz (T_p = 20 milliseconds). This digital circuit acts as a low pass filter blocking the AVR interrupt circuitry from responding to any of these additional edges.

Switch Debounce Circuit – a Simple Digital Low Pass Filter

From the Pre-lab

Appendix

How I Designed the Debounce Circuit

Here is a real world problem that I considered while designing my Debounce circuit.

Logic Levels

Between logic 0 and logic 1 there is an undefined region . The figure below shows TTL input and output voltage levels corresponding to logic 1 and 0 (source: Theory of TTL Logic Family).
Recommended Reading: Logic signal voltage levels

Logic Levels Based on Voltage Signal

Rise and Fall Times (Slew Rate)

Electrical signals have a finite period to transition through this region, technically known at rise and fall times or slew rate.

Slew Rate Graph

The table below provides data for propagation delay and slew rate for each of the families listed. Don’t allow digital logic slew rates to be slower than what is specified by the data sheet. All digital logic families will oscillate with slow rise times.

Propagation Delay & Slew Rate for Each Digital Logic Family

For some micro-controller inputs rise and fall times can be no more than 20 nsec. If this specification is violated the input may start to oscillate causing havoc within the device and ultimately destroying the input gate structure of the receiving gate.

Output Distorted due to Lower Slew Rate

The input circuits of MOS devices, like our AVR micro-controller, can be characterized as capacitive in nature (can be modeled to the first order by a capacitor). For some inputs this capacitance can be as great as 10 pF (pico = 10^-12). Now, let us assume an external pull-up resistor of 10 KΩ. Given this information we come up with a “back of the envelope” calculated time constant (RC) of 100 nsec.

Clearly, we have a problem. I solved this problem by adding a TTL device between the switch and the micro-controller. The input of the 74ALS74 can be characterized as resistive in nature (can be modeled by a resistor). Combined with a pull-up resistance (10 KΩ) the input problem is ameliorated.

The output of the 74ALS74 TTL device goes directly to the input of the AVR micro-controller solving our slew rate problem. This new faster circuit however introduces its own problems as discussed in the next section.

Interrupts and 16-bit Timer/Counter 1: Atmel AVR Timers and Interrupts

Reading

The AVR Microcontroller and Embedded Systems using Assembly and C
by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi

Section: 10.2

Interrupt Basics – Review –

ATmega328P Interrupt Vector Table

ATmega328P Enabling an Interrupt – Timer/Counter 1

• All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register (SREG) in order to enable the interrupt.
  
  

  Figure 1: Status Register

• For example, to allow the Timer/Counter 1 Overflow flag (TOV1) to generate an interrupt you would set the Timer/Counter 1 Overflow Interrupt Enable (TOIE1) bit.
  
  

  Figure 2: Timer Interrupt Mask Register

• When Timer/Counter 1 Overflows (0xFFFF  0x0000) the TOV1 bit is set to 1.
  
  

  Figure 3: Timer/Counter 1 Interrupt Flag Register

• With global interrupt I-bit set and Timer/Counter 1’s Overflow Interrupt Enable TOIE1-bit set, when the Overflow TOV1-bit is set an interrupt will be generated and the Program Counter (PC) will be vectored to Flash Program Memory address 0x001A (see IVT Table on previous page). The AVR processor starts running the ISR.
• The TOV1 flag is automatically cleared at the beginning of the interrupt service routine. Alternatively, if you are polling the flag, it can be cleared by writing a logical one to it. The TIFR1 register is within the I/O address range (0x00 to 0x1F) of the Set Bit in I/O Register (SBI) Instruction.

Timer/Counter 1 Normal Mode – Design Example

See Lecture 9 for the design example.

ATmega328P Enabling Timer/Counter 1 Interrupt

// Jump over and Setup the Interrupt Vector Table
RST_VECT:

rjmp reset

// TIMER1 OVF vector = 0x001A, Sect 9.4 Interrupt Vectors in ATmega328P
.ORG OVF1addr

jmp TOVF1_ISR // Section 4.7 Reset and Interrupt Handling

; Set prescale and start Timer/Counter1

ldi r16,(1<<cs11)|(1<<cs10) //prescale of 64 sect 15.11.2
sts TCCR1B,r16 // Table 15-5 Clock Select Bit Description

ldi r16,0x0B // load value high byte (Sect 15.2-15.3)
sts TCNT1H,r16
ldi r16,0xDC // load value low byte
sts TCNT1L,r16

// Enable Local and Global Interrupts

ldi r16,(1<<toie1) //enable interrupts for timer1 OVF
sts TIMSK1,r16 // TIMSK1 Bit 0 – TOIE1
sei // Global Interrupt Enable

The Interrupt Service Routine (ISR)

; — Timer/Counter 1 Overflow Interrupt Service Routine —
; Called on Timer/Counter1 overflow TOV1
; TOV1 flag automatically cleared by AVR on interrupt
TOVF1_ISR:

push reg_F
in reg_F,SREG
push r16

; — 250 msec —

ldi r16,0x0B // load value high byte 0x0B
sts TCNT1H,r16
ldi r16,0xDC // load value low byte 0xDC
sts TCNT1L,r16

; — Blink Discrete LED —

ldi r16,0b10000000 // toggle LED
eor spiLEDS, r16
pop r16
out SREG,reg_F
pop reg_F
reti

; ——————————————————-

Figure 4: Timing Reference

Addressing Modes Part II: AVR Addressing Indirect

READING

The AVR Microcontroller and Embedded Systems using Assembly and C
by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi

Sections: 6.1, 6.3, 6.4

ADDRESSING MODES

• When loading and storing data we have several ways to “address” the data.
• The AVR microcontroller supports addressing modes for access to the Program memory (Flash) and Data memory (SRAM, Register file, I/O Memory, and Extended I/O Memory).

Figure 1: Load-Store Instructions Table

OPERAND LOCATIONS AND THE ATMEGA328P MEMORY MODEL

When selecting an addressing mode you should ask yourself where is the operand (data) located within the memory model of the AVR processor and when do I know its address (assembly time or at run time).

Figure 2: 8-bit AVR Instruction Set
Source: atmel.com

IMMEDIATE ADDRESSING MODE – A REVIEW

C++ Code

uint8_t foo; // 8-bit unsigned number, from 0 to 255
foo = 0x23;

Assembly Code

Data is encoded with the instruction. Operand is therefore located in Flash Program Memory. This is why technically our memory model is a Modified Harvard.

ldi r16, 0x23 // where ldi = 1110, Rd = 00002

// and constant K = 001000112

Figure 3: Encoded ldi Instruction

Notice that only four bits (dddd) are set aside for defining destination register Rd. This limits us to 2⁴ = 16 registers. The designers of the AVR processor chose registers 16 to 31 to be these registers (i.e., 16 ≤ Rd ≤ 31).

What is the machine code instruction for our ldi example?

DIRECT ADDRESSING MODE – A REVIEW

C++ Code

uint8_t foo, A = 0x23; // 8-bit unsigned number, from 0 to 255
foo = A;

Assembly Code

.DSEG
A: .BYTE 1
.CSEG
lds r16, A

Figure 4: Encoded Instructions Using Direct Addressing

THE X-REGISTER, Y-REGISTER, AND Z-REGISTER

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described here.

Figure 5: X, Y, and Z Registers Used for Indirect Addressing

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).

PROGRAM MEMORY INDIRECT

• The indirect addressing mode in all its forms is used when you will not know the location of the data you want until the program is running. For example, in our 7-segment decoder example, we do not know ahead of time which number (0 to F) we want to decode.

lpm Rd, Z

• Instruction Encoding

Figure 6: Encoded Instructions Using Indirect Addressing

TWO VIEWPOINTS

• You can look at the indirect addressing mode address as a word address with a byte selector (illustration on the left), or as a byte address (illustration on the right).
• The first viewpoint is correct from a computer engineering perspective (it is really how it is works). The second perspective is functionally equivalent and helps us visualize the computation of the indirect address as the sum of the base address plus an index.
• The most significant bit of the ZH:ZL is lost, to make space for the byte address in the least significant bit.

Addressing Mode Operation – Two Viewpoints

PROGRAM MEMORY INDIRECT WITH POST-INCREMENT

lpm r16, Z+

Instruction Encoding

Addressing Mode Operation

Figure 9: Indirect Addressing Diagram

PROGRAM MEMORY INDIRECT – EXAMPLE 1

ldi ZH, high(Table<<1) // Initialize Z-pointer (read next page)
ldi ZL, low(Table<<1)
lpm r16, Z // Load constant from Program
; Memory pointed to by Z (r31:r30)
…
Table:
.DW 0x063F // 0x3F is addressed when ZLSB = 0
// 0x06 is addressed when ZLSB = 1

Figure 10: Indirect Addressing

PRINCETON VERSUS MODIFIED HARVARD MEMORY MODELS

Princeton or Von Neumann Memory Model
Program and data share the same memory space. Processors used in all personal computers, like the Pentium, implement a von Neumann architecture.

Harvard Memory Model
As we have learned in the Harvard Memory Model, program and data memory are separated. The AVR processors among others including the Intel 8051 use this memory model. One advantage of the Harvard architecture for microcontrollers is that program memory can be wider than data memory. This allows the processor to implement more instructions while still working with 8-bit data. For the AVR processor program memory is 16-bits wide while data memory is only 8-bits.

You may have already noticed that when you single step your program in the simulator of AVR Studio the Program Counter is incremented by 1 each time most instructions are executed. No surprise there right? Wrong. The program memory of the AVR processor can also be accessed at the byte level. In most cases this apparent paradox is transparent to the operation of your program with one important exception. That important exception is occurs when you want to access data stored in program memory. It is this ability of the AVR processor to access data stored in program memory that makes it a “Modified” Harvard Memory Model.

When you access from program memory you will be working with byte addresses not words (16-bits). The assembler is not smart enough to know the difference and so when you ask for an address in program memory it returns its word address. To convert this word address into a byte address you need to multiply it by 2. Problematically we do this by using the shift left syntax of C++ to explicitly tell the assembler to multiply the word address by 2. Remember, when you shift left one place you are effectively multiplying by 2.

With this in mind, we would interpret the following AVR instruction as telling the AVR assembler to convert the word address of label beehives in program memory to a byte address and then to take the low order of the resulting value and put into the source operand of the instruction.

ldi ZL,low(beeHives<<1) // load word address of beeHives look-up

PROGRAM MEMORY INDIRECT – EXAMPLE 2

Program Memory Indirect is great for implementing look-up tables located in Flash program memory – including decoders (gray code → binary, hex → seven segment, …)

In this example I build a 7-segment decoder in software.

BCD_to_7SEG:

ldi r16, 0b00001111 // limit to least significant
and r0, r16 // nibble (4 bits)
ldi ZL,low(table<<1) // load address of look-up
ldi ZH,high(table<<1)
clr r1
add ZL, r0
adc ZH, r1
lpm spi7SEG, Z
ret

//__________ gfedcba ___ gfedcba ___ gfedcba
table: .DB 0b00111111, 0b00000110, 0b01011011, …
// ________________0 _________ 1 _________ 2

BIG ENDIAN VERSUS LITTLE ENDIAN – DEFINE BYTE

To help understand the difference between Big and Little Endian let’s take a closer look at how data is stored in Flash Program Memory. We will first look at the Define Byte (.DB) Assembly Directive and then at the Define Word (.DW) Assembly Directive.

Figure 12: Bytes are First Stored in Lower Byte of the Address

Each table entry (.DB) contains one byte. If we look at the first table entry we see 0b00111111 which corresponds to 3f in hexadecimal. Comparing this with the corresponding address and data fields on the left… Wait a minute – where did 06 come from? That the second entry in the table (0b00000110 = 06₁₆). The bytes are backwards and here is why.

There are two basic ways information can be saved in memory known as Big Endian and Little Endian. For Big Endian the most significant byte (big end) is saved in the lowest order byte; so 0x3f06 would be saved as bytes 0x3f and 0x06. For Little Endian the least significant byte (little end) is saved in the lowest order byte; so 0x3f06 is save as bytes 0x06 and 0x3f. As you hopefully have guessed by now the AVR processor is designed to work with data words saved as Little Endian.

BIG ENDIAN VERSUS LITTLE ENDIAN – DEFINE WORD

Now let’s take a closer look at how data is saved in program memory using the Define Word (.DW) Assembly Directive. For illustrative purposes we will look at a look-up table named beeHives.

Figure 13: Memory Window Shows that the Word is Stored “Little Endian” (The Lower Byte) First

Each table entry (.DW) contains two bytes (1 16-bit word). These two bytes provide the row and column of a room containing bees. For example with respect to the maze, the room in row 00 column 04 contains 1 bee. If we look at the first entry we see it contains 0x0400. Comparing this with the corresponding Program Memory Window in AVR Studio… Wait a minute – that looks backward. From reading about the .DB assembly directive can you discover why?

Working with Bits and Bytes: Logic Instructions and Programs

READING

The AVR Microcontroller and Embedded Systems using Assembly and C
by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi

Sections: 5.3, 5.4, 5.5

OVERVIEW

Clearing and Setting a Bit In …

Where	Instruction	Alternative	Notes
I/O (0 – 31)	cbi, sbi		Use with I/O Ports
SREG	cl{i,t,h,s,v,n,z,c} se{i,t,h,s,v,n,z,c}	bclr bset
Working with General Purpose Register Bits
Clearing and Setting a Byte	clr, ser
Clearing Bits	and, cbr	andi
Testing Bits	and		Also consider using sbrc, sbrs, sbic, sbis (see Control Transfer Lecture)
Testing a Bit	bst  brts, brtc
Testing a Byte	tst  breq, brne
Setting Bits	or, sbr	ori
Inserting a Bit Pattern	cbr  sbr	and  or
Complementing (Toggling) Bits	eor
Rotating Bits	rol, ror
Shifting Bits	lsl, lsr, asr
Swapping Nibbles	swap

SAMPLE APPLICATION – KNIGHT RIDER

Figure 1: Knight Rider Poster

KnightRider:

; See page 5 and 6 – Clearing and Setting Bits

clr r16 // start with r9 bit 6 set – LED 6
sbr r16, 0b10000000

; Q1: How could we have done this using 1 instruction?

ldi r17,(1<<sreg_t) equivalent=”” to=”” 0b01000000<=”” span=””></sreg_t)>

; See page 7 – Clearing and Setting a Bit in the AVR Status Register

clt // initialize T = 0, scan right

; See page 8 – Testing Bits
loop:

ldi r19, 0b100000001
and r19,r16 // test if LED hit is at an edge
breq contScan // continue scan if z = 0

; See page 9 – Toggling Bits

in r16,SREG // toggle T bit
eor r16, r17
out SREG,r16

; See page 10 – Rotating and Shifting Bits
contScan:

brts scanLeft // rotate right or left
lsr r16
rjmp cont

scanLeft:

lsl r16

cont:

mov spiLEDS, r16
call WriteDisplay
rcall Delay
rjmp loop

SAMPLE APPLICATION – BICYCLE LIGHT

Figure 2: Bicycle Light

A bicycle light has 5 LEDs.

BicycleLight1: A repeating pattern starts with the center LED turned ON. The center LED is then turned OFF, and the LEDs to the left and right of the center LED are turned ON. Each LED continues its scan to the left or right. Once the LEDs reach the end the pattern repeats itself. Using the CSULB shield, write a program to simulate this bicycle light.

BicycleLight2: Same as Bicycle1 except when LEDs reach the edge, they scan back to the center.

BicycleLight1:

clr r7 // turn off 7 segment

begin: ldi r16, 0x04 // scan register r16 = 4

mov r17, r16 // scan register r17 = 4
scan: mov r8, r16 // do not modify r16
cbr r17, 0x20 // r17 bit 5 = 1 at end of cycle
or r8, r17 // combine scan registers
rcall Delay
call WriteDisplay
lsr r16 // scan r16 right
lsl r17 // scan r17 left, r17 = 0 at end of cycle
brne scan // if r17 <> 0 then continue scan
rjmp begin // else start next cycle

BicycleLight2:

ldi r16, 0x08 // 000|0_1000 start just in from edges
ldi r17, 0x02 // 000|0_0010

scan: mov r8, r16

or r8, r17
rcall Delay
call WriteDisplay
lsl r17 // scan r17 left
lsr r16 // scan r16 right
brcc scan
rjmp BicycleLight2

CLEARING BITS

To clear a bit set the corresponding mask bit to 0
and source/dest register, mask register

Figure 3: AND Truth Table Where ‘A’ Determines Which Bit to Clear

Problem: Convert numeric ASCII value (‘0’ – ‘9’) to its
binary coded decimal (BCD) equivalent (0 – 9).

• What we have: ‘0’ to ‘9’ which equals 30₁₆ to 39₁₆
• What we want: 0 to 9 which equals 00₁₆ to 09₁₆

Solution: Mask out high-order nibble
lds r16, ascii_value
ldi r17, 0x0F
and r16, r17 // or simply andi
sts bcd_value, r16

An alternative to the and instruction is the Clear Bits in Register cbr instruction.

cbr source/dest register, mask bits

The cbr instruction clears the specified bits in the source/Destination Register (Rd). It performs the logical AND between the contents of register Rd and the complement of the constant mask (K). The result will be placed in register Rd.

Rd  Rd ∙ (0xFF – K)

Here is how the previous problem would be solved using the cbr instruction.

lds r16, ascii_value
cbr r16, 0xF0
sts bcd_value, r16

SETTING BITS

To set a bit set the corresponding mask bit to 0
or source/dest register, control register

Figure 4: OR Truth Table Where ‘A’ Determines Which Bit to Set

Example: Set to one (1) bits 4 and 2 in some port.
in r16, some_port
ldi r17, 0b00010100
or r16, r17 // or simply ori
out some_port, r16

An alternative to the or instruction is the Set Bits in Register sbr instruction.

sbr source/dest register, mask bits

The sbr instruction sets the specified bits in the source/Destination Register (Rd). It performs the logical ORI between the contents of register Rd and the constant control (K). The result will be placed in register Rd.

Rd  Rd + K

Here is how the previous problem would be solved using the cbr instruction.

in r16, some_port
sbr r16, 0b00010100
out some_port, r16

CLEARING AND SETTING A BIT IN THE AVR STATUS REGISTER

Figure 5: Status Register

AVR Instructions for Clearing and Setting SREG bits
cl{i,t,h,s,v,n,z,c} or bclr SREG_{I,T,H,S,V,N,Z,C} // defined in m328Pdef.inc
se{i,t,h,s,v,n,z,c} or bset SREG_{I,T,H,S,V,N,Z,C} // defined in m328Pdef.inc

Examples:
Disable all Interrupts

cli

Set T bit

set

TESTING BITS

Use the andi instruction to test if more than one bit is set
andi source/dest register, mask bits

Figure 6: By Setting ‘A,’ the Tested Bit Reveals if the Source Bit was Set

Example 1: Branch if bit 7 or bit 0 is set

// 7654 3210

lds r16, some_bits // 1000 0000  example
andi r16, 0b10000001 // 1000 0001
brbc SREG_Z, bit_set // 1000 0000 (alt. brne)

Example 2: Branch if bit 4 and bit 2 are clear

// 7654 3210

lds r16, some_bits // 1101 1001  example
andi r16, 0b00010100 // 0001 0100
brbs SREG_Z, bits_zero // 0001 0000 (alt. breq)

Consider using one of the “Skip if Bit” instructions if you only need to test one bit.

Review “Control Transfer” lecture material for details.

Use the tst instructions to test if a register is Zero or Minus.

Tests if a register is zero or negative. Performs a logical AND between a register and itself. The register will remain
unchanged.

Example: Branch if bear is in the forest
rcall inForest // returns false(r24 = 0) if bear is not in the forest
tst r24
breq not_in_forest // branch if r24 = 0

TOGGLING BITS

To toggle (complement) a bit set the corresponding mask bit to 1
eor source/dest register, mask register

Figure 7: EOR/XOR Truth Table Where ‘A’ Determines Which Bit to Toggle

Example: Toggle bits 5 and 3 of I/O-Port D.

//7654 3210

in r16, PORTD // 1101 1001  example
ldi r17, 0x28 // 0010 1000
eor r16, r17 // 1111 0001
out PORTD, r16

When toggling an I/O-Port bit, consider writing a one to the corresponding pin.

Review “AVR Peripherals” lecture material for details.

Example: Toggle bits 5 and 3 of I/O-Port D.
sbi PIND, PIND5 // equivalent to sbi 0x09, 5
sbi PIND, PIND3

When toggling a byte (8 bits), use the Complement instruction.

Example: Write TurnAround code snip-it (i.e., toggle SRAM variable dir)

// 7654 3210

lds r16, dir // 1101 1001  facing East
com r16 //_____ 0010 0110  facing West
cbr r16, 0xFC //1111 1100 clear unused bits (optional)
sts dir, r16 // 0000 0010

Question: How could you have complemented dir without modifying the other 6 bits?

ROTATING AND SHIFTING BITS

Rotate Instructions allow us to rearrange bits without losing information and to sequentially test bit (brcc, brcs). Shift instructions allow us to quickly multiply and/or divide signed and/or unsigned numbers by 2.

Figure 8: Rotate Left Diagram

Rotate Left through Carry

rol Rd

Shifts all bits in Rd one place to the left. The C Flag is shifted into bit 0 of Rd. Bit 7 is shifted into the C Flag. This operation, combined with LSL, effectively multiplies multi-byte signed and unsigned values by two.

Figure 9: Rotate Right Diagram

Rotate Right through Carry
ror Rd

Shifts all bits in Rd one place to the right. The C Flag is shifted into bit 7 of Rd. Bit 0 is shifted into the C Flag. This operation, combined with ASR, effectively divides multi-byte signed values by two. Combined with LSR it effectively divides multibyte unsigned values by two. The Carry Flag can be used to round the result.

Figure 10: Logical Shift Left Diagram

Logical Shift Left (Arithmetic Shift Left)
lsl Rd

Shifts all bits in Rd one place to the left. Bit 0 is cleared. Bit 7 is loaded into the C Flag of the SREG. This operation effectively multiplies signed and unsigned values by two.

Figure 11: Logical Shift Right Diagram

Logical Shift Right
lsr Rd

Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0 is loaded into the C Flag of the SREG. This operation effectively divides an unsigned value by two. The C Flag can be used to round the result.

Figure 12: Arithmetic Shift Right Diagram

Arithmetic Shift Right
asr Rd

Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C Flag of the SREG. This operation effectively divides a signed value by two without changing its sign. The Carry Flag can be used to round the result.

CLEARING AND SETTING A BIT IN ONE OF THE FIRST 32 I/O REGISTERS

Example: Pulse Clock input of Proto-Shield Debounce D Flip-flop (PORTD5). Assume currently at logic 0.

sbi PORTD, 5
cbi PORTD, 5

Figure 13: Address Table

SETTING A BIT PATTERN

Use the Clear Bits in Register cbr or functionally equivalent andi instruction in combination with the Set Bits in Register sbr to set a bit pattern in a register.

Problem: Convert a binary coded decimal (BCD) (0 – 9) number to its ASCII equivalent value (‘0’ – ‘9’).

• What we have: 0 to 9 which equals X0₁₆ to X9₁₆
  The X indicates that we do not know what is contained in this nibble.
• What we want: ‘0’ to ‘9’ which equals 30₁₆ to 39₁₆

Solution: Set high-order nibble to 3₁₆
lds r16, bcd_value
andi r16, 0x0F // clear most significant nibble
sbr r16, 0x30 // set bits 5 and 4
sts ascii_value, r16

What is Happening

QUESTIONS

1. What instruction is used to divide a signed number by 2?
2. What instruction is used to multiply an unsigned number by 2?
3. What instruction(s) would be used to convert a word pointer into a byte pointer? A word pointer is a register pair like Z containing the address of a 16-bit data (2 byte) word in an SRAM Table. A byte pointer is a register pair like Z containing the address of an 8-bit data byte in a corresponding SRAM Table. Assuming there is a one-to-one relationship between each word in the first table with a byte in the second table. And remembering that SRAM is always addressed at the Byte level, how would convert a pointer defined for the word table into a pointer defined for the byte table.

Appendix

Introduction to AVR Assembly Language Programming II: Stack Operations

“Those who are last now will be first then, and those who are first will be last.” -Matthew 20:16

READING

The AVR Microcontroller and Embedded Systems using Assembly and C
by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi

Section: 3.2

AVRBeginners.Net
Jumps, Calls and the Stack

WORKING WITH STACKS

• Stacks
  FIFO and LIFO
  SP
  Initialization
• LIFO Stack Operations (Push and Pop)
  Explicit push and pop
  
  

  Figure 1: Register Transfer Language

  Implicit rcall, call, icall, ret, reti

• Working with the Stack (3 questions and answers)
  Word Size: 1 byte
  Points At: Empty Byte
  Direction: Decrements stack by 2 for implicit (call) and by 1 for explicit (push) stack operations
• The Program Counter byte ordering on the SRAM stack is Big Endian.

STACK OPERATION ON A CALL INSTRUCTION

Figure 2: Pointer Counter in Flash Program Memory

AMAZING LAB DESIGN EXAMPLE

Figure 3: Address of Instructions in Flash Program Memory

CALL INSTRUCTION ENCODING

• All control transfer addressing modes modify the program counter.
• The Program Counter byte ordering on the SRAM stack is Big Endian.

Figure 4: JMP & CALL Machine Code Stored in Flash Program Memory

RCALL INSTRUCTION ENCODING

Figure 5: RJMP & RCALL Machine Code Stored in Flash Program Memory

RET INSTRUCTION ENCODING

Figure 6: RET Machine Code used to Move Pointer Counter

AVR Instruction Set Encoding

Reading

“AVR Instruction Set,” Section 6.4 “General Purpose Register File,” and Section 7.3 “SRAM Data Memory” in document doc0856 “The Program and Data Addressing Modes.”

Instruction Set Mapping

The Instruction Set of our AVR processor can be functionally divided (or classified) into: Data Transfer Instructions, Arithmetic and Logic Instructions, Bit and Bit-Test Instructions, Control Transfer (Branch) Instructions, and MCU Control Instructions.

While this functional division helps you quickly find the instruction you need when you are writing a program; it does not reflect how the designers of the AVR processor mapped an assembly instruction into a 16-bit machine instruction. For this task a better way to look at the instructions is from the perspective of their addressing mode. We will divide AVR instructions into the following addressing mode types.

Data Addressing Modes

• Direct Register Addressing, Single Register
• Direct Register Addressing, Two 32 General Purpose Registers Rd and Rr
• Direct Register Addressing, Two 16 and 8 General Purpose Registers Rd and Rr
• Direct I/O Addressing (including SREG)
• Direct I/O Addressing, First 32 I/O Registers
• Direct SRAM Data Addressing
• Immediate 8-bit Constant
• Immediate 6-bit and 4-bit Constant
• Indirect SRAM Data Addressing with Pre-decrement and Post-increment
• Indirect Program Memory Addressing (Atmel Program Memory Constant Addressing)

Control Transfer

• Direct
• Relative, Unconditional
• Relative, Conditional
• Indirect

MCU Control Instructions

ATmega328P Operand Locations

When selecting an addressing mode you should ask yourself where the operand is (data) located within the AVR processor.

DATA ADDRESSING MODES

DIRECT REGISTER ADDRESSING, SINGLE REGISTER

DIRECT REGISTER ADDRESSING, TWO OF 32 8-BIT GENERAL PURPOSE REGISTERS RD AND RR

Multiply

DIRECT I/O ADDRESSING (INCLUDING SREG)

DIRECT SRAM DATA ADDRESSING

IMMEDIATE

INDIRECT SRAM DATA WITH DISPLACEMENT

INDIRECT SRAM DATA ADDRESSING WITH PRE-DECREMENT AND POST-INCREMENT

INDIRECT PROGRAM MEMORY ADDRESSING (ATMEL PROGRAM MEMORY CONSTANT ADDRESSING)

CONTROL TRANSFER

DIRECT

All control transfer addressing modes modify the program counter.

Figure 11: JMP & CALL Machine Code Stored in Flash Program Memory

INDIRECT

Figure 12: Indirect Instructions Machine Code

RELATIVE

Figure 13: Relative Branching Machine Code Stored in Flash Program Memory

MCU CONTROL INSTRUCTIONS

PROGRAM DECODING – WHO AM I?

Addr  Machine Instruction

Who_Am_I #1:
0204 9a5d      ____ ____, ____ // I/O direct
0205 985d      ____ ____, ____ // I/O direct
0206 9508      ____

Who_Am_I #2:
01f8 934f      ____ ____ // Indirect SRAM Data Addressing
01f9 b74f      ____ ____, ____ // I/O Direct
01fa 930f      ____ ____ // Indirect SRAM Data Addressing
01fb 9180 0103 ____ ____, ____ // Direct SRAM Data Addressing
01fd 9100 0102 ____ ____, ____ // Direct SRAM Data Addressing
01ff 2380      ____ ____, ____ // Direct Register Addressing,
0200 910f      ____ ____ // Indirect SRAM Data Addressing
0201 bf4f      ____ ____, ____ // I/O Direct
0202 914f      ____ ____ // Indirect SRAM Data Addressing
0203 9508      ____

PROGRAM ENCODING – DISPLAY

display:

:
_________      lds work0, imageR
_________      lds spi7SEG, imageD
_________      or spi7SEG, work0
_________      call spiTx
:
_________      ret

PROGRAM ENCODING – TURN LEFT

; ————————–
; ——- Turn Left ——–
turnLeft:

_________      push reg_F
_________      in reg_F,SREG
:
_________      lds work0, dir // x = work0 bit 1, y = work0 bit 0
_________      bst work0,0    // store y into T
_________      bld work1,1    // load dir.1 from T (dir.1 = y)
_________      com work0      // store /x into T
_________      bst work0,1
_________      bld work1,0    // load dir.0 from T (dir.0 = /x)
_________      sts dir, work1
:
_________      out SREG, reg_F
_________      pop reg_F
_________      ret