Midterm II Review Questions
In addition to the following questions, I would recommend reviewing the Midterm 1 Load-Store Worksheet
Warning:
Your one-sided 8 ½ x 11 page of notes may not contain questions and answers or copy-pasted bullet-points. It may only contain technical information relevant to the ATmega processor and other coursework related material. The following questions are provided to help you prepare for the second midterm only.
ATmega328P Timers and Interrupts
1. A computer spends its whole life _________ and _________ instructions.
Answer
2. Where can you find the Interrupt Vector Table (IVT)?
Answer
3. How many words (16-bits) are reserved for each entry in the IVT?
Answer
4. While the global interrupt SREG bit I is cleared, both the Timer/Counter 1 Overflow bit is set (IVT Address IVT 0x001A) Timer1 OVF and an external interrupt is received (IVT Address 0x0002) INT0. Assuming the interrupt enable bit for both interrupts is set, what will happen when the global interrupt bit is set (enabled)?
Answer
5. In which register can you find the global interrupt enable bit?
Answer
6. How many bits need to be set for a Timer/Counter 1 Overflow interrupt to be triggered?
Answer
7. When an interrupt is triggered, what register is placed on the stack?
Answer
8. Why is this register saved?
Answer
9. Why is the first instruction executed, at address 0x0000, always a jump?
Answer
10. If the instruction at address 0x0000 is not a jump what ISR will be executed?
Answer
11. What triggers a Timer/Counter 1 Overflow Interrupt?
Answer
12. What immediately happens when an interrupt occurs?
Answer
13. Just before a Timer/Counter Overflow Interrupt is run, what IVT address needs to be placed in the program counter (PC)?
Answer
14. What is instruction is required to return from an Interrupt?
Answer
15. In what way is a ret instruction different from an reti instruction?
Answer
16. What is one of the last things and ISR does before it returns control to the interrupted program?
Answer
17. What is the first and second to last thing your ISR should do?
Answer
18. What is the last thing your ISR should do?
Answer
19. What is wrong with this instruction push SREG?
Answer
20. Where should your ISR save the SREG register?
Answer
21. Where should your ISR save general purpose registers modified by the ISR?
Answer
22. Upon return from an ISR and enabling the global interrupt flag ; the AVR processor finds another interrupt waiting to be executed. What will happen next?
Answer
23. How many bits would be required to encode the register direct addressing mode?
Answer
24. The immediate addressing mode can only access 16 of the 32 general purpose registers. How many bits would be required to encode the register used in this type of instruction?
Answer
25. The immediate addressing mode encodes the data (operand) with the instruction. How many bits would be required to encode the data?
Answer
AVR Addressing Modes including Indirect
1. You can find the operand for the immediate addressing mode in what type of memory?
Answer
2. You can find the operand for the direct addressing mode of an lds and sts instruction in what type of memory?
Answer
3. You can find the operand for the direct addressing mode of an in and out instruction in which address space(s)?
Answer
4. The address space of which two addressing modes overlap?
Answer
5. What addressing mode should you use if you want to look up a pre-defined value in a table (data is known at assembly time)?
Answer
6. What addressing mode should you use if you want to look up a value in a table (data is known at run time)?
Answer
7. What addressing mode is used for the source operand of an lpm instruction?
Answer
8. What register pair is found in the source operand address field of an lpm instruction?
Answer
9. What register numbers correspond to pre-defined mnemonics ZH:ZL?
Answer
10. What two addressing mode should you use if you want to work with a table of data located in SRAM (data is known at run time)?
Answer
11. What addressing mode is used for the source operand of an ld instruction?
Answer
12. Which three register pairs may be found in the source operand address field of an ld instruction?
Answer
13. What two 8-bit register mnemonics are used to define the X register pair?
Answer
14. What addressing mode is used for the destination operand address field of the instruction lpm r16, Z?
Answer
15. What register is both a source and a destination for the instruction add r16, r17?
Answer
16. Write a code snip-it to load the 3rd byte (index = 2) of data from a table (label = TABLE) located in Flash Program memory. Answer left up to the student.
17. What is wrong with this instruction lds r16, low(Table << 1)? The source operand address field is of the immediate addressing mode type.
Answer
18. I want to load the number 3316 into register 16. Why can I not use the instruction lds r16, 0x33 to do this?
Answer
19. What addressing mode is used for the destination operand address field of the instruction lds r16, 0x33?
Answer
20. The AVR processor saves bytes of data in Flash Program Memory using what memory byte ordering?
Answer
21. Big Endian saves what half of a 2 byte (16-bit) word in the first byte (lowest address)?
Answer
22. What addressing mode is great for implementing look-up tables in Flash Program Memory?
Answer
23. Build a program to convert a 4-bit gray-code number into binary. Solution left to the student
24. What instruction is used to divide a register by two?
Answer
25. Write a program to set a 32 byte buffer located in SRAM to the blank ‘’ ASCII character. Solution left to the student.
26. To modify the seven segment display on the proto-shield you must write to register 8 and do what?
Answer
AVR Branching and Looping
1. ISA is an abbreviation for what?
Answer
2. How many general purpose registers does the AVR processor have?
Answer
3. What is the mnemonic for the last AVR general purpose register?
Answer
4. All unconditional jump instructions using the relative addressing mode, utilize 12 bits to encode the distance the program is to jump relative to the program counter (PC). Given that this 12 bit number is saved using 2’s complement notation, what is the range in words (16-bits) that the AVR processor can jump for this type of instruction?
Answer
5. All conditional branch instructions using the relative addressing mode, utilize 7 bits to encode the distance the program is to branch relative to the program counter (PC). Given that this 7 bit number is saved using 2’s complement notation, what is the range in words (16-bits) that the AVR processor can branch for this type of instruction?
Answer
6. Which instructions do you typically find before a relative branch instruction? Compare and test instructions?
Answer
7. Compare and test instructions like cp, cpc, cpi, tst, bst do not modify any of the 32 general purpose registers. What register(s) do they modify?
Answer
8. What type of instruction typically follows a compare and test instruction, like cp, cpc, cpi, tst, bst?
Answer
9. Why does a compare or test instruction, typically precede a conditional branch instruction?
Answer
10. What is wrong with the following two sequential instructions? cpi r16, 0x33,followed by rjmp there
Answer
11. Why is the following two sequential instructions silly?
Answer
12. What bit(s) within SREG are never modified by a compare or test instruction?
Answer
13. What is wrong with the following two sequential instructions? cpi r16, 0x33,followed by brts there
Answer
14. Assuming that r16 contains the value 0x33. What value would be in r16 after the instruction cpi r16, 0x33 is executed?
Answer
15. Assuming that r16 contains the value 0x33. What value would be in r16 after the instruction subi r16, 0x33 is executed?
Answer
16. Assuming that r16 contains the value 0x33. What 1-bit value would be contained in the Z-bit in SREG after the instruction cpi r16, 0x33 is executed?
Answer
17. What type of instruction never modify bits within the SREG register?
Answer
18. Write the code to implement the following flow-chart
Solution left to the student
19. Write the code to implement the following flow-chart
Solution left to the student
AVR Bits and Bytes
1. What instruction(s) could you use to clear the carry bit?
Answer
2. What instruction would you use to clear PORT D bit 3?
Answer
3. What is wrong with this the instruction cbi TIMSK1, 0?
Answer
4. Write
an instruction to clear bit 4, 2, and 0 in register 16.
Answer
5. Write an instruction to clear bit 4, 2, and 0 in register 16 without using the cbr instruction.
Answer
6. Write an instruction to set bit 4, 2, and 0 in register 16.
Answer
7. Write an instruction to set bit 4, 2, and 0 in register 16 without using the sbr instruction.
Answer
8. What is wrong with this instruction to toggle bit 4, 2, and 0 in register 16?
Answer
9. Write an instruction sequence to toggle bit 4, 2, and 0 in register 16.
Answer
10. Write an instruction sequence to set bits 4, 2, and 0 to 1012 in register 16, without modifying any other bits.
Answer
11. Write an instruction to set bits 7, 6, 5, 4, 3, 2, 1, 0 in register 16, without using the sbr or or instruction.
Answer
12. Write a program to wire switch 0 to the decimal point of the 7-segment display on the proto-shield.
Solution left to the student
13. Pulse Clock input of Proto-Shield Debounce D Flip-flop (PORTD bit 5). Assume currently at logic 0.
Answer
14. What logical instruction is implemented by the tst instruction?
Answer
15. What is the difference between the and and the tst instruction?
Answer
16. What does the cp instruction have in common with the tst instruction?
Answer
17. Assuming register 16 contains 0x00. What would the Z-bit be set/cleared to after executing the instruction tst r16?
Answer
18. What instruction is used to disable all interrupts?
Answer
19. How many operand(s ) does the tst instruction have?
Answer
20. Complete the following Boolean expression representing the operation of a the tst r16 instruction.
r16 ___ r16
Answer
21. What instruction would be used to implement the logic operation represented by the question mark (?) in Figure 1 (Shown below)?
Answer
22. What phrase best describes the operation shown in Figure 1 box A?
Answer
23. What word best
describes the operation shown in Figure 1 box B?
Figure 1
Answer
24.
Write the code needed to implement the following circuit.
